Datasheet > 97ULPA877AKLFT

97ULPA877AKLFT

更新时间： 2024-01-25 17:29:30

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
15页	183K
描述
Clock Driver

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技术参数
数据手册

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97ULPA877AKLFT 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.84
Base Number Matches：	1

97ULPA877AKLFT 数据手册

ICS97ULPA877A

Integrated

Circuit

Systems,Inc.

1.8V Low-Power Wide-Range Frequency Clock Driver

Pin Configuration

RecommendedApplication:

•

DDR2 Memory Modules / Zero Delay Board Fan Out

Provides complete DDR DIMM logic solution with

ICSSSTU32864/SSTUF32864/SSTUF32866/

SSTUA32864/SSTUA32866/SSTUA32S868/

SSTUA32S865/SSTUA32S869

ProductDescription/Features:

•

Low skew, low jitter PLL clock driver

1 to 10 differential clock distribution (SSTL_18)

Feedback pins for input to output synchronization

Spread Spectrum tolerant inputs

Auto PD when input signal is at a certain logic state

52-Ball BGA

SwitchingCharacteristics:

Top View

•

Period jitter:40ps (DDR2-400/533)

30ps (DDR2-667/800)

Half-period jitter: 60ps (DDR2-400/533)

50ps (DDR2-667/800)

OUTPUT - OUTPUT skew: 40ps (DDR2-400/533)

30ps (DDR2-667/800)

CYCLE - CYCLE jitter 40ps

CLKT1

CLKC1

CLKC2

CLKT2

CLK_INT

CLK_INC

AGND

AVDD

CLKT3

CLKC3

CLKT0

GND

VDDQ

GND

CLKC0

GND

CLKC5

GND

CLKT5

GND

CLKT6

CLKC6

CLKC7

CLKT7

VDDQ

GND

CLKC9

FB_INT

FB_INC

FB_OUTC

FB_OUTT

CLKT8

VDDQ

GND

CLKC4

GND

CLKT4

GND

CLKT9

CLKC8

Block Diagram

CLKT0

CLKC0

LD* or OE

Powerdown

Control and

Test Logic

CLKT1

CLKC1

LD*, OS or OE

AV_DD

CLKT2

CLKC2

PLL bypass

LD*

VDDQ

CLKC2

CLKT2

CLK_INT

CLK_INC

VDDQ

CLKC7

CLKT3

CLKC3

CLKT7

VDDQ

FB_INT

FB_INC

FB_OUTC

FB_OUTT

VDDQ

CLKT4

CLKC4

CLKT5

CLKC5

ICS97ULPA877A

AGND

AVDD

VDDQ

CLK_INT

CLKT6

CLKC6

CLK_INC

10K-100k

CLKT7

CLKC7

PLL

GND ¹⁰

GND

CLKT8

CLKC8

FB_INT

FB_INC

CLKT9

CLKC9

* The Logic Detect (LD) powers down the device when a

logic low is applied to both CLK_INT and CLK_INC.

FB_OUTT

FB_OUTC

40-Pin MLF

1088B—01/18/06

12 3 4 5 6 7...15

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