Datasheet > 97U877KLF-T

97U877KLF-T

更新时间： 2024-01-20 15:14:57

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
13页	129K
描述
Clock Driver

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数据手册

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97U877KLF-T 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.84	Base Number Matches：	1

97U877KLF-T 数据手册

ICS97U877

Pin Descriptions

Terminal

Name

Electrical

Characteristics

Description

AGND

AV_DD

Analog Ground

Analog power

Ground

1.8 V nominal

CLK_INT

CLK_INC

FB_INT

Clock input with a (10K-100K Ohm) pulldown resistor

Complentary clock input with a (10K-100K Ohm) pulldown resistor

Feedback clock input

Differential input

FB_INC

FB_OUTT

FB_OUTC

Complementary feedback clock input

Feedback clock output

Differential input

Differential output

LVCMOS input

Ground

Complementary feedback clock output

Output Enable (Asynchronous)

Output Select (tied to GND or V_DDQ

Ground

)

GND

V_DDQ

Logic and output power

Clock outputs

1.8V nominal

CLKT[0:9]

CLKC[0:9]

Differential outputs

Complementary clock outputs

No ball

The PLL clock buffer, ICS97U877, is designed for aV_DDQof 1.8V, a AV_DDof 1.8V and differential data input and output

levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF.

ICS97U877 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential

pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC).

The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the

LVCMOS program pins (OE, OS) and the Analog Power input (AVDD).When OE is low, the outputs (except FB_OUTT/

FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a

program pin that must be tied to GND orV_DDQ.When OS is high, OE will function as described above.When OS is low,

OEhasnoeffectonCLKT7/CLKC7(theyarefreerunninginadditiontoFB_OUTT/FB_OUTC).WhenAV_DDisgrounded,

the PLL is turned off and bypassed for test purposes.

When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic

detection circuit onthedifferentialinputs, independent from theinput buffers, willdetect thelogic lowlevelandperform

alow powerstatewherealloutputs, thefeedbackandthePLLareOFF.Whentheinputstransitionfrombothbeinglogic

low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL

willobtainphaselockbetweenthefeedbackclockpair(FB_INT, FB_INC)andtheinputclockpair(CLK_INT, CLK_INC)

within the specified stabilization time t_STAB

The PLL in ICS97U877 clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,

FB_INC)toprovidehigh-performance, low-skew, low-jitteroutputdifferentialclocks(CLKT[0:9], CLKC[0:9]).ICS97U877

is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.

ICS97U877 is characterized for operation from 0°C to 70°C.

0792A—04/15/04

123 4 5 6 7...13

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与97U877KLF-T相关器件

型号	品牌	描述	获取价格	数据表
97U877K-T	IDT	Clock Driver	获取价格
97U877YHLF-T	IDT	PLL Based Clock Driver, 97U Series, 10 True Output(s), 0 Inverted Output(s), PBGA52, LEAD	获取价格
97U877YKLF-T	IDT	PLL Based Clock Driver, 97U Series, 10 True Output(s), 0 Inverted Output(s), PQCC40, LEAD	获取价格
97U877YK-T	IDT	PLL Based Clock Driver, 97U Series, 10 True Output(s), 0 Inverted Output(s), PQCC40, PLAST	获取价格
97ULP877BH	IDT	CABGA-52, Tray	获取价格
97ULP877BHLF-T	IDT	PLL Based Clock Driver, 97ULP Series, 10 True Output(s), 0 Inverted Output(s), PBGA52, LEA	获取价格

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