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93732AFLFT PDF预览

93732AFLFT

更新时间: 2024-11-26 07:19:11
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 98K
描述
SSOP-28, Reel

93732AFLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:0.209 INCH, GREEN, MO-150, SSOP-28针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.79
系列:93732输入调节:STANDARD
JESD-30 代码:R-PDSO-G28JESD-609代码:e3
长度:10.2 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A湿度敏感等级:1
功能数量:1反相输出次数:6
端子数量:28实输出次数:6
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP28,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:2.5 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.1 ns座面最大高度:2 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm
最小 fmax:340 MHz

93732AFLFT 数据手册

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ICS93732  
Integrated  
Circuit  
Systems,Inc.  
LowCostDDRPhaseLockLoopZeroDelayBuffer  
Recommended Application:  
Pin Configuration  
DDR Zero Delay Clock Buffer  
GND  
DDRC0  
DDRC5  
DDRT5  
DDRC4  
DDRT4  
VDD  
SDATA  
N/C  
FB_INT  
FB_OUTT  
N/C  
DDRT3  
DDRC3  
GND  
DDRT0  
VDD  
DDRT1  
DDRC1  
GND  
SCLK  
CLK_INT  
N/C  
VDDA  
GND  
VDD  
DDRT2  
DDRC2  
ProductDescription/Features:  
Low skew, low jitter PLL clock driver  
Max frequency supported = 266MHz (DDR 533)  
I2C for functional and output control  
Feedback pins for input to output synchronization  
Spread Spectrum tolerant inputs  
3.3V tolerant CLK_INT input  
Switching Characteristics:  
CYCLE - CYCLE jitter (66MHz): <120ps  
CYCLE - CYCLE jitter (>100MHz): <65ps  
CYCLE - CYCLE jitter (>200MHz): <75ps  
OUTPUT - OUTPUT skew: <100ps  
DUTY CYCLE: 49.5% - 50.5%  
28-pin 209mil SSOP  
Block Diagram  
Functionality  
INPUTS  
OUTPUTS  
PLL State  
AVDD CLK_INT CLKT CLKC FB_OUTT  
2.5V  
(nom)  
FBB__OOUUTTTT  
L
L
H
L
L
on  
on  
Control  
DDDRRTT00  
DDDRRCC00  
SCCLLKK  
2.5V  
(nom)  
Logic  
SDATA  
H
H
H
DDDRRTT11  
DDDRRCC11  
DDDRRTT22  
DDDRRCC22  
DDDRRTT33  
DDDRRCC33  
FB_INT  
PLLLL  
DDDRRTT44  
DDDRRCC44  
CLLKK__IINNTT  
DDDRRTT55  
DDDRRCC55  
0578J—06/20/08  

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