5秒后页面跳转
93735AF-T PDF预览

93735AF-T

更新时间: 2024-11-25 20:02:51
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
9页 155K
描述
PLL Based Clock Driver, 93735 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.300 INCH, MO-118, SSOP-48

93735AF-T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:SSOP
包装说明:SSOP,针数:48
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.7系列:93735
输入调节:STANDARDJESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:15.875 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:48
实输出次数:10最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):225传播延迟(tpd):3.68 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.098 ns
座面最大高度:2.8 mm最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:7.5 mm
Base Number Matches:1

93735AF-T 数据手册

 浏览型号93735AF-T的Datasheet PDF文件第2页浏览型号93735AF-T的Datasheet PDF文件第3页浏览型号93735AF-T的Datasheet PDF文件第4页浏览型号93735AF-T的Datasheet PDF文件第5页浏览型号93735AF-T的Datasheet PDF文件第6页浏览型号93735AF-T的Datasheet PDF文件第7页 
DATASHEET  
ICS93735  
Low Cost DDR Phase Lock Loop Zero Delay Buffer  
Description  
DDR Zero Delay Clock Buffer  
Output Features  
Low skew, low jitter PLL clock driver  
I2C for functional and output control  
Feedback pins for input to output synchronization  
Spread Spectrum tolerant inputs  
3.3V tolerant CLK_INT input  
FuntionalityTable  
Key Specifications  
INPUTS  
OUTPUTS  
CLKC  
PEAK - PEAK jitter (66MHz): <120ps  
PEAK - PEAK jitter (>100MHz): <75ps  
CYCLE - CYCLE jitter (66MHz):<110ps  
CYCLE - CYCLE jitter (>100MHz):<65ps  
OUTPUT - OUTPUT skew: <100ps  
Output Rise and Fall Time: 650ps - 950ps  
DUTY CYCLE: 49.5% - 50.5%  
PLL State  
AVDD  
2.5V (nom)  
2.5V (nom)  
2.5V (nom)  
GND  
CLK_INT  
CLKT  
L
H
FB_OUTT  
L
H
H
L
L
H
on  
on  
off  
< offset freq* offset freq* offset freq* offset freq*  
L
L
H
H
L
L
H
Bypassed/off  
Bypassed/off  
GND  
H
* The offset frequency is ~ 20 MHz, varying somewhat from part to part.  
48-pin SSOP package  
Available in RoHS compliant packaging  
Funtional Block Diagram  
Pin Configuration  
FB_OUTT  
CLKT0  
CLKC0  
CLKT1  
CLKC1  
Control  
SCLK  
CLKT2  
CLKC2  
Logic  
SDATA  
CLKT3  
CLKC3  
CLKT4  
CLKC4  
CLKT5  
CLKC5  
FB_INT  
PLL  
CLKT6  
CLKC6  
CLK_INT  
CLKT7  
CLKC7  
CLKT8  
CLKC8  
48-pin SSOP  
CLKT9  
CLKC9  
IDTTM/ICSTM Low Cost DDR Phase Lock Loop Zero Delay Buffer  
ICS93735  
REV F 02/11/07  

与93735AF-T相关器件

型号 品牌 获取价格 描述 数据表
93735F-LFT IDT

获取价格

Clock Driver, PDSO48
93735YFLF-T IDT

获取价格

PLL Based Clock Driver, 93735 Series, 10 True Output(s), 10 Inverted Output(s), PDSO48
93735YF-T IDT

获取价格

PLL Based Clock Driver, 10 True Output(s), 10 Inverted Output(s), PDSO48
93738AFLF IDT

获取价格

Clock Driver
93738AFLFT IDT

获取价格

Clock Driver
93738FT IDT

获取价格

Clock Driver, PDSO48
93738YFT IDT

获取价格

Low Skew Clock Driver, 11 True Output(s), 11 Inverted Output(s), PDSO48
9374-24-01-00-0600 ECS

获取价格

Board Stacking Connector
9374-24-01-01-0600 ECS

获取价格

Board Stacking Connector
9374-24-01-10-0600 ECS

获取价格

Board Stacking Connector