Datasheet > 93735YF-T

93735YF-T

更新时间： 2024-11-26 09:59:31

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
7页	126K
描述
PLL Based Clock Driver, 10 True Output(s), 10 Inverted Output(s), PDSO48

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

93735YF-T 数据手册

ICS93735

Integrated

Circuit

Systems, Inc.

DDR Phase Lock Loop Zero Delay Clock Buffer

RecommendedApplication:

Pin Configuration

DDR Zero Delay Clock Buffer

Product Description/Features:

•

Low skew, low jitter PLL clock driver

Max frequency supported = 266MHz (DDR 533)

I²C for functional and output control

Feedback pins for input to output synchronization

•

Spread Spectrum tolerant inputs

3.3V tolerant CLK_INT input

Switching Characteristics:

•

CYCLE - CYCLE jitter (66MHz): <120ps

CYCLE - CYCLE jitter (>100MHz): <65ps

CYCLE - CYCLE jitter (>200MHz): <75ps

OUTPUT - OUTPUT skew: <100ps

Output Rise and Fall Time: 500ps - 700ps

DUTY CYCLE: 49.5% - 50.5%

48-Pin SSOP

Functionality

INPUTS

OUTPUTS

PLL State

AVDD

2.5V (nom)

GND

CLK_INT

CLKT

CLKC

FB_OUTT

off

< offset freq* offset freq* offset freq* offset freq*

Bypassed/off

GND

* The offset frequency is ~ 20 MHz, varying somewhat from part to part.

Block Diagram

FB_OUTT

CLKT0

CLKC0

CLKT1

CLKC1

Control

Logic

CLKT2

CLKC2

SCLK

SDATA

CLKT3

CLKC3

CLKT4

CLKC4

CLKT5

CLKC5

FB_INT

PLL

CLKT6

CLKC6

CLK_INT

CLKT7

CLKC7

CLKT8

CLKC8

CLKT9

CLKC9

0579E—08/06/03

12 3 4 5 6 7

中文翻译

下载PDF

与93735YF-T相关器件

型号	品牌	获取价格	描述	数据表
93738AFLF	IDT	获取价格	Clock Driver
93738AFLFT	IDT	获取价格	Clock Driver
93738FT	IDT	获取价格	Clock Driver, PDSO48
93738YFT	IDT	获取价格	Low Skew Clock Driver, 11 True Output(s), 11 Inverted Output(s), PDSO48
9374-24-01-00-0600	ECS	获取价格	Board Stacking Connector
9374-24-01-01-0600	ECS	获取价格	Board Stacking Connector
9374-24-01-10-0600	ECS	获取价格	Board Stacking Connector
9374-24-09-01-1200	ECS	获取价格	Board Stacking Connector
9374-24-09-10-1200	ECS	获取价格	Board Stacking Connector
9374-24-14-00-1200	ECS	获取价格	Board Stacking Connector