Datasheet > 93738AFLFT

93738AFLFT

更新时间： 2024-11-26 09:47:35

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
9页	95K
描述
Clock Driver

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中文翻译

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数据手册

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93738AFLFT 数据手册

ICS93738

Integrated

Circuit

Systems, Inc.

DDR and SDRAM Buffer

Recommended Application:

DDR & SDRAM fanout buffer, for VIA P4X/KT266/333

chipsets.

Pin Configuration

FB_OUT

VDD3.3_2.5

SEL_DDR*

VDD2.5

GND

DDRT11

DDRC11

DDRT10

DDRC10

VDD2.5

GND

DDRT9

DDRC9

VDD2.5

PD#*

GND

DDRT0_SDRAM0

DDRC0_SDRAM1

DDRT1_SDRAM2

DDRC1_SDRAM3

VDD3.3_2.5

ProductDescription/Features:

•

Low skew, fanout buffer

1 to 12 differential clock distribution

I²C for functional and output control

Feedback pin for input to output synchronization

Supports up to 4 DDR DIMMs or 3 SDRAM DIMMs +

2 DDR DIMMs

GND

DDRT2_SDRAM4

DDRC2_SDRAM5

VDD3.3_2.5

BUF_IN

GND

DDRT3_SDRAM6

DDRC3_SDRAM7

VDD3.3_2.5

•

Frequency supports up to 200MHz (DDR400)

Supports Power Down Mode for power

mananagement

GND

DDRT8

DDRC8

VDD2.5

GND

DDRT7

DDRC7

DDRT6

DDRC6

GND

•

CMOS level control signal input

GND

DDRT4_SDRAM8

DDRC4_SDRAM9

DDRT5_SDRAM10

DDRC5_SDRAM11

VDD3.3_2.5

SwitchingCharacteristics:

•

OUTPUT - OUTPUT skew: <100ps SDRAM

OUTPUT - OUTPUT skew: <150ps DDR

Output Rise and Fall Time for DDR outputs: 600ps -

950ps

DUTY CYCLE: 47% - 53% DDR

DUTY CYCLE: 45%- 55% SDRAM

SDATA

SCLK

48-Pin SSOP

*Internal Pull-up Resistor of 120K to VDD

Block Diagram

Functionality

VDD

3.3_2.5

FB_OUT

MODE

PIN 48

4, 5, 6, 7, 10, 11, 15,

16, 19, 20, 21, 22

DDRT0_SDRAM0

DDRC0_SDRAM1

BUF_IN

DDR

Mode

These outputs will be

DDR outputs

DDRT1_SDRAM2

DDRC1_SDRAM3

SEL_DDR=1

SEL_DDR=0

2.5V

3.3V

DDRT2_SDRAM4

DDRC2_SDRAM5

These outputs will be

standard SDRAM

outputs

SCLK

DDR/SD

Mode

Control

SDATA

DDRT3_SDRAM6

DDRC3_SDRAM7

Logic

SEL_DDR*

PD#

DDRT4_SDRAM8

DDRC4_SDRAM9

DDRT5_SDRAM10

DDRC5_SDRAM11

DDRT(11:6)

DDRC (11:6)

0689B—01/12/06

12 3 4 5 6 7...9

中文翻译

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