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93735AFLF-T PDF预览

93735AFLF-T

更新时间: 2024-11-25 20:02:51
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
9页 155K
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93735AFLF-T 数据手册

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DATASHEET  
ICS93735  
Low Cost DDR Phase Lock Loop Zero Delay Buffer  
Description  
DDR Zero Delay Clock Buffer  
Output Features  
Low skew, low jitter PLL clock driver  
I2C for functional and output control  
Feedback pins for input to output synchronization  
Spread Spectrum tolerant inputs  
3.3V tolerant CLK_INT input  
FuntionalityTable  
Key Specifications  
INPUTS  
OUTPUTS  
CLKC  
PEAK - PEAK jitter (66MHz): <120ps  
PEAK - PEAK jitter (>100MHz): <75ps  
CYCLE - CYCLE jitter (66MHz):<110ps  
CYCLE - CYCLE jitter (>100MHz):<65ps  
OUTPUT - OUTPUT skew: <100ps  
Output Rise and Fall Time: 650ps - 950ps  
DUTY CYCLE: 49.5% - 50.5%  
PLL State  
AVDD  
2.5V (nom)  
2.5V (nom)  
2.5V (nom)  
GND  
CLK_INT  
CLKT  
L
H
FB_OUTT  
L
H
H
L
L
H
on  
on  
off  
< offset freq* offset freq* offset freq* offset freq*  
L
L
H
H
L
L
H
Bypassed/off  
Bypassed/off  
GND  
H
* The offset frequency is ~ 20 MHz, varying somewhat from part to part.  
48-pin SSOP package  
Available in RoHS compliant packaging  
Funtional Block Diagram  
Pin Configuration  
FB_OUTT  
CLKT0  
CLKC0  
CLKT1  
CLKC1  
Control  
SCLK  
CLKT2  
CLKC2  
Logic  
SDATA  
CLKT3  
CLKC3  
CLKT4  
CLKC4  
CLKT5  
CLKC5  
FB_INT  
PLL  
CLKT6  
CLKC6  
CLK_INT  
CLKT7  
CLKC7  
CLKT8  
CLKC8  
48-pin SSOP  
CLKT9  
CLKC9  
IDTTM/ICSTM Low Cost DDR Phase Lock Loop Zero Delay Buffer  
ICS93735  
REV F 02/11/07  

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