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935347049557

更新时间： 2024-11-11 03:52:19

品牌	Logo	应用领域
恩智浦 - NXP		微控制器
页数	文件大小	规格书
76页	992K
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RISC Microcontroller

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935347049557 数据手册

Document Number MPC5746C

Rev. 6, 11/2018

NXP Semiconductors

Data Sheet: Technical Data

MPC5746C

MPC5746C Microcontroller

Datasheet

Features

• 32-channel eDMA controller with multiple transfer

request sources using DMAMUX

• 1 × 160 MHz Power Architecture® e200z4 Dual issue,

32-bit CPU

• Boot Assist Flash (BAF) supports internal flash

programming via a serial link (SCI)

– Single precision floating point operations

– 8 KB instruction cache and 4 KB data cache

– Variable length encoding (VLE) for significant code

density improvements

• Analog

– Two analog-to-digital converters (ADC), one 10-bit

and one 12-bit

• 1 x 80 MHz Power Architecture® e200z2 Single issue,

32-bit CPU

– Three analog comparators

– Cross Trigger Unit to enable synchronization of

ADC conversions with a timer event from the

eMIOS or from the PIT

– Using variable length encoding (VLE) for

significant code size footprint reduction

• End to end ECC

• Communication

– All bus masters, for example, cores, generate a

single error correction, double error detection

(SECDED) code for every bus transaction

– SECDED covers 64-bit data and 29-bit address

– Four Deserial Serial Peripheral Interface (DSPI)

– Four Serial Peripheral interface (SPI)

– 16 serial communication interface (LIN) modules

– Eight enhanced FlexCAN3 with FD support

– Four inter-IC communication interface (I2C)

– ENET complex (10/100 Ethernet) that supports

Multi queue with AVB support, 1588, and MII/

RMII

• Memory interfaces

– 3 MB on-chip flash memory supported with the

flash memory controller

– 3 x flash memory page buffers (3-port flash memory

controller)

– Dual-channel FlexRay controller

– 384 KB on-chip SRAM across three RAM ports

• Audio

– Synchronous Audio Interface (SAI)

– Fractional clock dividers (FCD) operating in

conjunction with the SAI

• Clock interfaces

– 8-40 MHz external crystal (FXOSC)

– 16 MHz IRC (FIRC)

– 128 KHz IRC (SIRC)

• Configurable I/O domains supporting FlexCAN,

LINFlexD, Ethernet, and general I/O

– 32 KHz external crystal (SXOSC)

– Clock Monitor Unit (CMU)

– Frequency modulated phase-locked loop (FMPLL)

– Real Time Counter (RTC)

• Supports wake-up from low power modes via the

WKPU controller

• On-chip voltage regulator (VREG)

• System Memory Protection Unit (SMPU) with up to 32

region descriptors and 16-byte region granularity

• Debug functionality

– e200z2 core:NDI per IEEE-ISTO 5001-2008

• 16 Semaphores to manage access to shared resources

Class3+

• Interrupt controller (INTC) capable of routing

interrupts to any CPU

– e200z4 core: NDI per IEEE-ISTO 5001-2008 Class

• Crossbar switch architecture for concurrent access to

peripherals, flash memory, and RAM from multiple

bus masters

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

12 3 4 5 6 7...76

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