Datasheet > 935347682557

935347682557

更新时间： 2024-11-07 19:35:11

品牌	Logo	应用领域
恩智浦 - NXP		微控制器外围集成电路
页数	文件大小	规格书
83页	1299K
描述
RISC Microcontroller

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935347682557 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.59
uPs/uCs/外围集成电路类型：	MICROCONTROLLER, RISC	Base Number Matches：	1

935347682557 数据手册

Document Number S32K1XX

Rev. 8, 06/2018

NXP Semiconductors

Data Sheet: Advance Information

S32K1XX

S32K1xx Data Sheet

Notes

• Power management

– Low-power Arm Cortex-M4F/M0+ core with

excellent energy efficiency

• Technical information for S32K118 device is

preliminary, until this device achieves qualification.

– Power Management Controller (PMC) with multiple

power modes: HSRUN, RUN, STOP, VLPR, and

VLPS. Note: CSEc (Security) or EEPROM writes/

erase will trigger error flags in HSRUN mode (112

MHz) because this use case is not allowed to

execute simultaneously. The device will need to

switch to RUN mode (80 Mhz) to execute CSEc

(Security) or EEPROM writes/erase.

• Following two are the available attachments with

Datasheet:

– S32K1xx_Orderable_Part_Number_ List.xlsx

– S32K1xx_Power_Modes_Configuration.xlsx

Key Features

• Operating characteristics

– Voltage range: 2.7 V to 5.5 V

– Ambient temperature range: -40 °C to 105 °C for

HSRUN mode, -40 °C to 125 °C for RUN mode

– Clock gating and low power operation supported on

specific peripherals.

• Memory and memory interfaces

• Arm™ Cortex-M4F/M0+ core, 32-bit CPU

– Supports up to 112 MHz frequency (HSRUN mode)

with 1.25 Dhrystone MIPS per MHz

– Arm Core based on the Armv7 Architecture and

Thumb®-2 ISA

– Up to 2 MB program flash memory with ECC

– 64 KB FlexNVM for data flash memory with ECC

and EEPROM emulation. Note: CSEc (Security) or

EEPROM writes/erase will trigger error flags in

HSRUN mode (112 MHz) because this use case is

not allowed to execute simultaneously. The device

will need to switch to RUN mode (80 MHz) to

execute CSEc (Security) or EEPROM writes/erase.

– Up to 256 KB SRAM with ECC

– Integrated Digital Signal Processor (DSP)

– Configurable Nested Vectored Interrupt Controller

(NVIC)

– Single Precision Floating Point Unit (FPU)

– Up to 4 KB of FlexRAM for use as SRAM or

EEPROM emulation

– Up to 4 KB Code cache to minimize performance

impact of memory access latencies

• Clock interfaces

– 4 - 40 MHz fast external oscillator (SOSC)

– 48 MHz Fast Internal RC oscillator (FIRC)

– 8 MHz Slow Internal RC oscillator (SIRC)

– 128 kHz Low Power Oscillator (LPO)

– Up to 112 MHz (HSRUN) System Phased Lock

Loop (SPLL)

– QuadSPI with HyperBus™ support

• Mixed-signal analog

– Up to two 12-bit Analog-to-Digital Converter

(ADC) with up to 32 channel analog inputs per

module

– Up to 50 MHz DC external square wave input clock

– Real Time Counter (RTC)

– One Analog Comparator (CMP) with internal 8-bit

Digital to Analog Converter (DAC)

• Debug functionality

– Serial Wire JTAG Debug Port (SWJ-DP) combines

– Debug Watchpoint and Trace (DWT)

– Instrumentation Trace Macrocell (ITM)

– Test Port Interface Unit (TPIU)

– Flash Patch and Breakpoint (FPB) Unit

• Human-machine interface (HMI)

– Up to 156 GPIO pins with interrupt functionality

– Non-Maskable Interrupt (NMI)

This document contains information on a pre-production product. Specifications

and pre-production information herein are subject to change without notice.

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