Datasheet > 935350817557

935350817557

更新时间： 2024-09-21 20:05:03

品牌	Logo	应用领域
恩智浦 - NXP		外围集成电路
页数	文件大小	规格书
79页	3156K
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Microprocessor

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935350817557 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	unknown	uPs/uCs/外围集成电路类型：	MICROPROCESSOR
Base Number Matches：	1

935350817557 数据手册

Document Number S32R274

Rev. 5, 04/2019

NXP Semiconductors

Data Sheet: Technical Data

S32R274

S32R274/S32R264 Series

Data Sheet

Supports S32R274K, S32R274J,

S32R264K and S32R264J

Features

• Functional Safety

– Enables up to ASIL-D applications

– FCCU for fault collection and fault handling

– MEMU for memory error management

– Safe eDMA controller

– Self-Test Control Unit (STCU2)

– Error Injection Module (EIM)

– On-chip voltage monitoring

• On-chip modules available within the device include

the following features:

• Safety core: Power Architecture® e200Z4 32-bit CPU

with checker core

• Dual issue computation cores: Power Architecture®

e200Z7 32-bit CPU

– Clock Monitor Unit (CMU)

• 2 MB on-chip code flash (FMC flash) with ECC

• 1.5 MB on-chip SRAM with ECC

• Security

– Cryptographic Security Engine (CSE2)

– Supports censorship and life-cycle management

• RADAR processing

– Signal Processing Toolbox (SPT) for RADAR signal

processing acceleration

– Cross Timing Engine (CTE) for precise timing

generation and triggering

– Waveform generation module (WGM) for chirp

ramp generation

– 4x 12-bit ΣΔ-ADC with 10 MSps

– One DAC with 10 MSps

• Timers

– Two Periodic Interval Timers (PIT) with 32-bit

counter resolution

– Three System Timer Module (STM)

– Three Software Watchdog Timers (SWT)

– Two eTimer modules with 6 channels each

– One FlexPWM module for 12 PWM signals

• Communication Interfaces

– MIPICSI2 interface to connect external ADCs

– Two Serial Peripheral interface (SPI) modules

– One LINFlexD module

• Memory Protection

– Each core memory protection unit provides 24

entries

– Two inter-IC communication interface (I2C)

modules

– Data and instruction bus system memory protection

unit (SMPU) with 16 region descriptors each

– Register protection

– One dual-channel FlexRay module with 128

message buffers

– Three FlexCAN modules with configurable buffers -

CAN FD optionally supported on 2 FlexCAN

modules

– One ENET MAC supporting MII/RMII/RGMII

interface

– ZipWire high-speed serial communication

• Clock Generation

– 40 MHz external crystal (XOSC)

– 16 MHz Internal oscillator (IRCOSC)

– Dual system PLL with one frequency modulated

phase-locked loop (FMPLL)

– Low-jitter PLL to ΣΔ-ADC and DAC clock

generation (not supported on SC66760x devices)

• Debug Functionality

– 4-pin JTAG interface and Nexus/Aurora interface

for serial high-speed tracing

– e200Z7 core and e200Z4 core: Nexus development

interface (NDI) per IEEE-ISTO 5001-2012 Class 3+

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

12 3 4 5 6 7...79

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