Document Number S32K1XX
Rev. 6, 01/2018
NXP Semiconductors
Data Sheet: Product Preview
S32K1XX
S32K1xx Data Sheet
Caution
• Memory and memory interfaces
– Up to 2 MB program flash memory with ECC
– 64 KB FlexNVM for data flash memory with ECC
and EEPROM emulation. Note: No write or erase
access to Security (CSEc) or EEPROM is allowed
when device is running at HSRUN mode (112
MHz).
– Up to 256 KB SRAM with ECC
– Up to 4 KB of FlexRAM for use as SRAM or
EEPROM emulation
• S32K146, S32K116, and S32K118 specific
information is preliminary until these devices are
qualified.
Key Features
• Operating characteristics
– Voltage range: 2.7 V to 5.5 V
– Ambient temperature range: -40 °C to 105 °C for
HSRUN, -40 °C to 125 °C for RUN
– Up to 4 KB Code cache to minimize performance
impact of memory access latencies
– QuadSPI with HyperBus™ support
• Arm™ Cortex-M4F/M0+ core, 32-bit CPU
– Supports up to 112 MHz frequency (HSRUN) with
1.25 Dhrystone MIPS per MHz
• Mixed-signal analog
– Arm Core based on the Armv7 Architecture and
Thumb®-2 ISA
– Integrated Digital Signal Processor (DSP)
– Configurable Nested Vectored Interrupt Controller
(NVIC)
– Up to two 12-bit Analog-to-Digital Converter
(ADC) with up to 32 channel analog inputs per
module
– One Analog Comparator (CMP) with internal 8-bit
Digital to Analog Converter (DAC)
– Single Precision Floating Point Unit (FPU)
• Debug functionality
• Clock interfaces
– Serial Wire JTAG Debug Port (SWJ-DP) combines
– Debug Watchpoint and Trace (DWT)
– Instrumentation Trace Macrocell (ITM)
– Test Port Interface Unit (TPIU)
– 4 - 40 MHz fast external oscillator (SOSC)
– 48 MHz Fast Internal RC oscillator (FIRC)
– 8 MHz Slow Internal RC oscillator (SIRC)
– 128 kHz Low Power Oscillator (LPO)
– Up to 112 MHz (HSRUN) System Phased Lock
Loop (SPLL)
– Flash Patch and Breakpoint (FPB) Unit
• Human-machine interface (HMI)
– Up to 50 MHz DC external square wave input clock
– Real Time Counter (RTC)
– Up to 156 GPIO pins with interrupt functionality
– Non-Maskable Interrupt (NMI)
• Power management
• Communications interfaces
– Low-power Arm Cortex-M4F/M0+ core with
excellent energy efficiency
– Up to three Low Power Universal Asynchronous
Receiver/Transmitter (LPUART) modules with
DMA support and low power availability
– Up to three Low Power Serial Peripheral Interface
(LPSPI) modules with DMA support and low power
availability
– Up to two Low Power Inter-Integrated Circuit
(LPI2C) modules with DMA support and low power
availability
– Power Management Controller (PMC) with multiple
power modes: HSRUN, Run, Stop, VLPR, and
VLPS. Note: No write or erase access to Security
(CSEc) or EEPROM is allowed when device is
running at HSRUN mode (112 MHz).
– Supports peripheral specific clock gating. Only
specific peripherals remain working in low power
modes.
– Up to three FlexCAN modules (with optional CAN-
FD support)
– FlexIO module for flexible and high performance
serial interfaces
This document contains information on a product under development. NXP
reserves the right to change or discontinue this product without notice.
Preliminary