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935325879557

更新时间： 2024-09-21 14:40:35

品牌	Logo	应用领域
恩智浦 - NXP		外围集成电路
页数	文件大小	规格书
127页	2439K
描述
Microprocessor

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935325879557 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.68
Is Samacsys：	N	uPs/uCs/外围集成电路类型：	MICROPROCESSOR
Base Number Matches：	1

935325879557 数据手册

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MPC8535EEC

Rev. 7, 07/2015

MPC8535E

MPC8535E PowerQUICC III

Integrated Processor

Hardware Specifications

MAPBGA–783

29 mm x 29 mm

• High-performance, 32-bit e500 core, scaling up to

1.25 GHz, that implements the Power Architecture®

technology

– Support for various Ethernet physical interfaces: GMII,

TBI, RTBI, RGMII, MII, RGMII, RMII, and SGMII

– Support TCP/IP acceleration and QOS features

– MAC address recognition and RMON statistics support

– Support ARP parsing and generating wake-up events

based on the parsing results while in deep sleep mode

– Support accepting and storing packets while in deep

sleep mode

– 36-bit physical addressing

– Double-precision embedded floating point APU using

64-bit operands

– Embedded vector and scalar single-precision

floating-point APUs using 32- or 64-bit operands

– Memory management unit (MMU)

• High-speed interfaces (multiplexed) supporting:

– Two PCI Express interfaces

• Integrated L1/L2 cache

– L1 cache—32-Kbyte data and 32-Kbyte instruction

– L2 cache—512-Kbyte (8-way set associative)

• DDR2/DDR3 SDRAM memory controller with full ECC

support

– PCI Express 1.0a compatible

– One x4/x2/x1 PCI Express interface

–

Two x2/x1 ports

– One SGMII interface

– One Serial ATA (SATA) controller supports SATA I and

SATA I data rates

– One 64-bit/32-bit data bus

– Up to 250-MHz clock (500-MHz data rate)

– Supporting up to 16 Gbytes of main memory

– Using ECC, detects and corrects all single-bit errors and

detects all double-bit errors and all errors within a nibble

– Invoke a level of system power management by

asserting MCKE SDRAM signal on-the-fly to put the

memory into a low-power sleep mode

• PCI 2.2 compatible PCI controller

• Two universal serial bus (USB) dual-role controllers

comply with USB specification revision 2.0

• 133-MHz, 32-bit, enhanced local bus (eLBC) with memory

controller

• Enhanced secured digital host controller (eSDHC) used for

SD/MMC card interface

– Both hardware and software options to support

battery-backed main memory

– Support boot capability from eSDHC

• Integrated four-channel DMA controller

• Integrated security engine (SEC) optimized to process all

the algorithms associated with IPsec, IKE, SSL/TLS,

iSCSI, SRTP, IEEE Std 802.16e™, and 3GPP.

– XOR engine for parity checking in RAID storage

applications

• Dual I C and dual universal asynchronous

receiver/transmitter (DUART) support

• Programmable interrupt controller (PIC)

• Power management, low standby power

• Enhanced Serial peripheral interfaces (eSPI)

– Support boot capability from eSPI

• Two enhanced three-speed Ethernet controllers (eTSECs)

with SGMII support

– Support Doze, Nap, Sleep, Jog, and Deep Sleep mode

– PMC wake on: LAN activity, USB connection or remote

wakeup, GPIO, internal timer, or external interrupt event

• System performance monitor

– Three-speed support (10/100/1000 Mbps)

– Two IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x,

IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab, and

IEEE Std 1588™-compatible controllers

• IEEE Std 1149.1™-compatible, JTAG boundary scan

• 783-pin FC-PBGA package, 29 mm × 29 mm

Freescale reserves the right to change the detail specifications as may be required

to permit improvements in the design of its products.

12 3 4 5 6 7...127

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