Datasheet > 935321725557

935321725557

更新时间： 2024-09-20 21:05:39

品牌	Logo	应用领域
恩智浦 - NXP		外围集成电路
页数	文件大小	规格书
70页	924K
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Digital Signal Processor

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935321725557 技术参数

生命周期：	Active	Reach Compliance Code：	unknown
uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER	Base Number Matches：	1

935321725557 数据手册

Document Number: MSC8256

Rev. 6, 7/2013

Freescale Semiconductor

Data Sheet

MSC8256

Six-Core Digital Signal

Processor

FC-PBGA–783

29 mm × 29 mm

•

Six StarCore SC3850 DSP subsystems, each with an SC3850

DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,

unified 512 Kbyte L2 cache configurable as M2 memory in

64 Kbyte increments, memory management unit (MMU),

extended programmable interrupt controller (EPIC), two

general-purpose 32-bit timers, debug and profiling support,

low-power Wait, Stop, and power-down processing modes, and

ECC/EDC support.

Chip-level arbitration and switching system (CLASS) that

provides full fabric non-blocking arbitration between the cores

and other initiators and the M2 memory, shared M3 memory,

DDR SRAM controllers, device configuration control and status

registers, and other targets.

•

High-speed serial interface that supports two Serial RapidIO

interfaces, one PCI Express interface, and two SGMII interfaces

(multiplexed). The Serial RapidIO interfaces support 1x/4x

operation up to 3.125 Gbaud with a single messaging unit and two

DMA units. The PCI Express controller supports 32- and 64-bit

addressing, x4, x2, and x1 link.

QUICC Engine technology subsystem with dual RISC

processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction

RAM, supporting two communication controllers for two Gigabit

Ethernet interfaces (RGMII or SGMII), to offload scheduling

tasks from the DSP cores, and an SPI.

I/O Interrupt Concentrator consolidates all chip maskable

interrupt and non-maskable interrupt sources and routes then to

INT_OUT, NMI_OUT, and the cores.

UART that permits full-duplex operation with a bit rate of up to

6.25 Mbps.

•

1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can

be turned off to save power.

96 Kbyte boot ROM.

•

Three input clocks (one global and two differential).

Five PLLs (three global and two Serial RapidIO PLLs).

Two DDR controllers with up to a 400 MHz clock (800 MHz data

rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to

four banks (two per controller) and support for DDR2 and DDR3.

DMA controller with 32 unidirectional channels supporting 16

memory-to-memory channels with up to 1024 buffer descriptors

per channel, and programmable priority, buffer, and multiplexing

configuration. It is optimized for DDR SDRAM.

Up to four independent TDM modules with programmable word

size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion,

up to 62.5 Mbps data rate for each TDM link, and with glueless

interface to E1 or T1 framers that can interface with

H-MVIP/H.110 devices, TSI, and codecs such as AC-97.

Two general-purpose 32-bit timers for RTOS support per SC3850

core, four timer modules with four 16-bit fully programmable

timers, and eight software watchdog timers (SWT).

Eight programmable hardware semaphores.

•

Up to 32 virtual interrupts and a virtual NMI asserted by simple

write access.

•

I²C interface.

Up to 32 GPIO ports, sixteen of which can be configured as

external interrupts.

•

Boot interface options include Ethernet, Serial RapidIO interface,

I²C, and SPI.

•

Supports standard JTAG interface

Low power CMOS design, with low-power standby and

power-down modes, and optimized power-management circuitry.

45 nm SOI CMOS technology.

•

12 3 4 5 6 7...70

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