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935298743118

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935298743118 数据手册

74HC138-Q100; 74HCT138-Q100

3-to-8 line decoder/demultiplexer; inverting

Rev. 2 — 26 January 2015

Product data sheet

1. General description

The 74HC138-Q100; 74HCT138-Q100 decodes three binary weighted address inputs

(A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three

enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and

E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to

32 lines) decoder with just four ‘138’ ICs and one inverter. The ‘138’ can be used as an

eight output demultiplexer by using one of the active LOW enable inputs as the data input

and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the

use of current limiting resistors to interface inputs to voltages in excess of V_CC

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Complies with JEDEC standard no. 7A

 Input levels:

 For 74HC138-Q100: CMOS level

 For 74HCT138-Q100: TTL level

 Demultiplexing capability

 Multiple input enable for easy expansion

 Ideal for memory chip select decoding

 Active LOW mutually exclusive outputs

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 Multiple package options

12 3 4 5 6 7...17

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