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934041730118 PDF预览

934041730118

更新时间: 2024-11-16 21:11:43
品牌 Logo 应用领域
恩智浦 - NXP 驱动接口集成电路
页数 文件大小 规格书
13页 138K
描述
IC BUF OR INV BASED PRPHL DRVR, Peripheral Driver

934041730118 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:,Reach Compliance Code:unknown
风险等级:5.84接口集成电路类型:BUFFER OR INVERTER BASED PERIPHERAL DRIVER
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

934041730118 数据手册

 浏览型号934041730118的Datasheet PDF文件第2页浏览型号934041730118的Datasheet PDF文件第3页浏览型号934041730118的Datasheet PDF文件第4页浏览型号934041730118的Datasheet PDF文件第5页浏览型号934041730118的Datasheet PDF文件第6页浏览型号934041730118的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
PowerMOS transistor  
Logic level TOPFET  
BUK109-50DL  
DESCRIPTION  
QUICK REFERENCE DATA  
Monolithic temperature and  
overload protected logic level power  
MOSFET in a 3 pin plastic surface  
mount envelope, intended as a  
general purpose switch for  
automotive systems and other  
applications.  
SYMBOL  
PARAMETER  
MAX.  
UNIT  
VDS  
ID  
Continuous drain source voltage  
Continuous drain current  
50  
26  
75  
150  
60  
V
A
W
˚C  
m  
PD  
Tj  
Total power dissipation  
Continuous junction temperature  
Drain-source on-state resistance  
RDS(ON)  
APPLICATIONS  
IISL  
Input supply current  
VIS = 5 V  
650  
µA  
General controller for driving  
lamps  
motors  
solenoids  
heaters  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Vertical power DMOS output  
stage  
Low on-state resistance  
Overload protection against  
over temperature  
Overload protection against  
short circuit load  
Latched overload protection  
reset by input  
DRAIN  
O/V  
CLAMP  
POWER  
INPUT  
MOSFET  
5 V logic compatible input level  
Control of power MOSFET  
and supply of overload  
protection circuits  
RIG  
LOGIC AND  
derived from input  
PROTECTION  
Lower operating input current  
permits direct drive by  
micro-controller  
ESD protection on input pin  
Overvoltage clamping for turn  
off of inductive loads  
SOURCE  
Fig.1. Elements of the TOPFET.  
PINNING - SOT404  
PIN CONFIGURATION  
SYMBOL  
PIN  
1
DESCRIPTION  
D
S
mb  
TOPFET  
input  
drain  
2
I
P
3
source  
2
mb drain  
1
3
June 1996  
1
Rev 1.000  

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