Datasheet > 8T49N203A-018NLGI

8T49N203A-018NLGI

更新时间： 2024-11-24 19:01:59

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
40页	1222K
描述
PLL/Frequency Synthesis Circuit, PQCC40

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8T49N203A-018NLGI 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	QCCN, LCC40,.24SQ,20	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.44	JESD-30 代码：	S-PQCC-N40
端子数量：	40	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCN	封装等效代码：	LCC40,.24SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER
电源：	2.5/3.3 V	认证状态：	Not Qualified
子类别：	PLL or Frequency Synthesis Circuits	最大供电电流 (Isup)：	284 mA
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	Base Number Matches：	1

8T49N203A-018NLGI 数据手册

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FemtoClock® NG Universal Frequency

Translator

IDT8T49N203I

DATA SHEET

General Description

Features

The IDT8T49N203I is a highly flexible FemtoClock® NG general

purpose, low phase noise Universal Frequency Translator /

Synthesizer with alarm and monitoring functions suitable for

networking and communications applications. It is able to generate

any output frequency in the 0.98MHz - 312.5MHz range and most

output frequencies in the 312.5MHz - 1,300MHz range (see Table 3

for details). A wide range of input reference clocks and a range of

low-cost fundamental mode crystal frequencies may be used as the

source for the output frequency.

• Fourth generation FemtoClock® NG technology

• Universal Frequency Translator (UFT) / Frequency Synthesizer

• Two outputs, individually programmable as LVPECL or LVDS

• Both outputs may be set to use 2.5V or 3.3V output levels

• Programmable output frequency: 0.98MHz up to 1,300MHz

• Zero ppm frequency translation

• Two differential inputs support the following input types:

LVPECL, LVDS, LVHSTL, HCSL

The IDT8T49N203I has three operating modes to support a very

broad spectrum of applications:

• Input frequency range: 8kHz - 710MHz

• Crystal input frequency range: 16MHz - 40MHz

¹⁾•^FrS^ey^qn^ut^ehⁿe^cs^yize^Ss^yno^tu^ht^ep^suⁱt^zefr^requencies from a 16MHz - 40MHz

• Two factory-set register configurations for power-up default state

• Power-up default configuration pin or register selectable

• Configurations customized via One-Time Programmable ROM

fundamental mode crystal.

• Fractional feedback division is used, so there are no

requirements for any specific crystal frequency to produce the

desired output frequency with a high degree of accuracy.

• Settings may be overwritten after power-up via I C

• I C Serial interface for register programming

²⁾•^HA^igp^hp^-Blic^aaⁿt^dio^wnⁱs^d:^thPC^FrI^eE^qx^up^erⁿe^cs^ys,^TC^raoⁿm^slp^au^toti^rng, General Purpose

• RMS phase jitter at 155.52MHz, using a 40MHz crystal LVDS

Output (12kHz - 20MHz): 439fs (typical), Low Bandwidth Mode

(FracN)

• Translates any input clock in the 16MHz - 710MHz frequency

range into any supported output frequency.

• RMS phase jitter at 400MHz, using a 40MHz crystal

(12kHz - 40MHz):285fs (typical), Synthesizer Mode (Integer FB)

• This mode has a high PLL loop bandwidth in order to track input

reference changes, such as Spread-Spectrum Clock

modulation, so it will not attenuate much jitter on the input

reference.

• Output supply voltage modes:

V_CC/V_CCA/V_CCO

3.3V/3.3V/3.3V

3.3V/3.3V/2.5V (LVPECL only)

2.5V/2.5V/2.5V

³⁾•^LoA^wp^-p^Bli^acaⁿt^dio^wn^ids^t:^hN^Fe^rt^ew^qo^ur^ekⁿin^cg^y&^TrC^ano^sm^lam^tou^rnications.

• Translates any input clock in the 8kHz -710MHz frequency

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package

Pin Assignment

range into any supported output frequency.

• This mode supports PLL loop bandwidths in the 10Hz - 580Hz

range and makes use of an external crystal to provide

significant jitter attenuation.

This device provides two factory-programmed default power-up

configurations burned into One-Time Programmable (OTP) memory.

The configuration to be used is selected by the CONFIG pin. The two

configurations are specified by the customer and are programmed by

IDT during the final test phase from an on-hand stock of blank

devices. The two configurations may be completely independent of

one another.

30 29 28 27

23 22 21

26 25 24

CLK_ACTIVE

IDT8T49N203I

S_A0

S_A1

CONFIG

SCLK

SDATA

V^CC

LF0

40 Lead VFQFN

6mm x 6mm x 0.925mm

K Package

LF1

One usage example might be to install the device on a line card with

two optional daughter cards: an OC-12 option requiring a 622.08MHz

LVDS clock translated from a 19.44MHz input and a Gigabit Ethernet

option requiring a 125MHz LVPECL clock translated from the same

19.44MHz input reference.

VEE

V^CCA

Top View

HOLDOVER

CLK0BAD

CLK1BAD

XTALBAD

PLL_BYPASS

To implement other configurations, these power-up default settings

9 10

6 7

can be overwritten after power-up using the I C interface and the

device can be completely reconfigured. However, these settings

would have to be re-written next time the device powers-up.

The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.

Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice

IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012

12 3 4 5 6 7...40

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与8T49N203A-018NLGI相关器件

型号	品牌	获取价格	描述	数据表
8T49N203A-019NLGI	IDT	获取价格	PLL/Frequency Synthesis Circuit, PQCC40
8T49N203A-023NLGI	IDT	获取价格	PLL/Frequency Synthesis Circuit, PQCC40
8T49N203A-024NLGI	IDT	获取价格	PLL/Frequency Synthesis Circuit, PQCC40
8T49N203A-025NLGI	IDT	获取价格	PLL/Frequency Synthesis Circuit, PQCC40
8T49N203A-027NLGI	IDT	获取价格	PLL/Frequency Synthesis Circuit, PQCC40
8T49N203A-028NLGI	IDT	获取价格	PLL/Frequency Synthesis Circuit, PQCC40
8T49N203A-028NLGI8	IDT	获取价格	PLL/Frequency Synthesis Circuit, PQCC40
8T49N203A-029NLGI	IDT	获取价格	PLL/Frequency Synthesis Circuit, PQCC40
8T49N203A-029NLGI8	IDT	获取价格	PLL/Frequency Synthesis Circuit, PQCC40
8T49N203A-DDDNLGI	IDT	获取价格	Clock Generator, 1300MHz, CMOS, 6 X 6 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VJJC-3, M

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