FemtoClock® NG Universal Frequency
Translator
IDT8T49N203I
DATA SHEET
General Description
Features
The IDT8T49N203I is a highly flexible FemtoClock® NG general
purpose, low phase noise Universal Frequency Translator /
Synthesizer with alarm and monitoring functions suitable for
networking and communications applications. It is able to generate
any output frequency in the 0.98MHz - 312.5MHz range and most
output frequencies in the 312.5MHz - 1,300MHz range (see Table 3
for details). A wide range of input reference clocks and a range of
low-cost fundamental mode crystal frequencies may be used as the
source for the output frequency.
• Fourth generation FemtoClock® NG technology
• Universal Frequency Translator (UFT) / Frequency Synthesizer
• Two outputs, individually programmable as LVPECL or LVDS
• Both outputs may be set to use 2.5V or 3.3V output levels
• Programmable output frequency: 0.98MHz up to 1,300MHz
• Zero ppm frequency translation
• Two differential inputs support the following input types:
LVPECL, LVDS, LVHSTL, HCSL
The IDT8T49N203I has three operating modes to support a very
broad spectrum of applications:
• Input frequency range: 8kHz - 710MHz
• Crystal input frequency range: 16MHz - 40MHz
1) •FrSeyqnutehnecsyizeSsynotuhtepsuitzefrrequencies from a 16MHz - 40MHz
• Two factory-set register configurations for power-up default state
• Power-up default configuration pin or register selectable
• Configurations customized via One-Time Programmable ROM
fundamental mode crystal.
• Fractional feedback division is used, so there are no
requirements for any specific crystal frequency to produce the
desired output frequency with a high degree of accuracy.
2
• Settings may be overwritten after power-up via I C
2
• I C Serial interface for register programming
2) •HAigphp-Blicaantdiownisd:thPCFrIeEqxupernecsys,TCraonmslpautotirng, General Purpose
• RMS phase jitter at 155.52MHz, using a 40MHz crystal LVDS
Output (12kHz - 20MHz): 439fs (typical), Low Bandwidth Mode
(FracN)
• Translates any input clock in the 16MHz - 710MHz frequency
range into any supported output frequency.
• RMS phase jitter at 400MHz, using a 40MHz crystal
(12kHz - 40MHz):285fs (typical), Synthesizer Mode (Integer FB)
• This mode has a high PLL loop bandwidth in order to track input
reference changes, such as Spread-Spectrum Clock
modulation, so it will not attenuate much jitter on the input
reference.
• Output supply voltage modes:
VCC/VCCA/VCCO
3.3V/3.3V/3.3V
3.3V/3.3V/2.5V (LVPECL only)
2.5V/2.5V/2.5V
3) •LoAwp-pBliacantdiownidst:hNFertewqoureknincgy&TrCanosmlamtournications.
• Translates any input clock in the 8kHz -710MHz frequency
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Pin Assignment
range into any supported output frequency.
• This mode supports PLL loop bandwidths in the 10Hz - 580Hz
range and makes use of an external crystal to provide
significant jitter attenuation.
This device provides two factory-programmed default power-up
configurations burned into One-Time Programmable (OTP) memory.
The configuration to be used is selected by the CONFIG pin. The two
configurations are specified by the customer and are programmed by
IDT during the final test phase from an on-hand stock of blank
devices. The two configurations may be completely independent of
one another.
30 29 28 27
23 22 21
26 25 24
31
20
nc
CLK_ACTIVE
nc
nc
32
33
34
35
36
37
38
39
40
19
18
17
16
15
14
13
12
11
IDT8T49N203I
S_A0
S_A1
CONFIG
SCLK
SDATA
VCC
LF0
40 Lead VFQFN
6mm x 6mm x 0.925mm
K Package
LF1
One usage example might be to install the device on a line card with
two optional daughter cards: an OC-12 option requiring a 622.08MHz
LVDS clock translated from a 19.44MHz input and a Gigabit Ethernet
option requiring a 125MHz LVPECL clock translated from the same
19.44MHz input reference.
VEE
VCCA
Top View
HOLDOVER
CLK0BAD
CLK1BAD
XTALBAD
PLL_BYPASS
nc
To implement other configurations, these power-up default settings
1
2
3
4
8
9 10
5
6 7
2
can be overwritten after power-up using the I C interface and the
device can be completely reconfigured. However, these settings
would have to be re-written next time the device powers-up.
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012
1
©2012 Integrated Device Technology, Inc.
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