®
FemtoClock NG Ultra-Performance
8T49N240
Datasheet
Jitter Attenuator
Description
Features
▪ Four differential outputs
The 8T49N240 is a fractional-feedback single channel jitter
attenuator with frequency translation. It is equipped with three
integer and one fractional output dividers, allowing the generation
of up to four different output frequencies, ranging from 8kHz to
867MHz. These frequencies are completely independent of the
input reference frequencies and the crystal reference frequency.
The outputs may select among LVPECL, LVDS, HCSL, or
LVCMOS output levels.
▪ Excellent jitter performance:
— < 200fs (typical) RMS (including spurs):
12kHz to 20MHz for integer-divider outputs in jitter
attenuator mode or in fractional-feedback synthesizer mode
▪ Operating Modes: Synthesizer, Jitter Attenuator
▪ Operates from a 10MHz to 54MHz fundamental-mode crystal
▪ Initial holdover accuracy of +50ppb
The 8T49N240 accepts up to two differential or single-ended input
clocks and a fundamental-mode crystal input. The internal PLL
can lock to either of the input reference clocks or just to the crystal
to behave as a frequency synthesizer. The PLL can use the
second input for redundant backup of the primary input reference,
but in this case, both input clock references must be integer
related in frequency.
▪ Accepts up to two LVPECL, LVDS, LVHSTL, or LVCMOS input
clocks
— Accepts frequencies ranging from 8kHz to 875MHz
— Auto and manual clock selection with hitless switching
— Clock input monitoring including support for gapped clocks
▪ Phase-slope limiting and fully hitless switching options to
The device supports hitless reference switching between input
clocks. The device monitors both input clocks for Loss of Signal
(LOS), and generates an alarm when an input clock failure is
detected. Automatic and manual hitless reference switching
options are supported. LOS behavior can be set to support
gapped or un-gapped clocks.
control output clock phase transients
▪ Three outputs generate LVPECL / LVDS / HCSL clocks, one
output generates LVPECL / LVDS / HCSL / LVCMOS clocks
— Output frequencies ranging from 8kHz up to 867MHz
(differential)
— Output frequencies ranging from 8kHz to 250MHz
(LVCMOS)
The 8T49N240 supports holdover. The holdover has an initial
accuracy of ±50ppB from the point where the loss of all applicable
input reference(s) has been detected. It maintains a historical
average operating point for the PLL that may be returned to in
holdover at a limited phase slope.
— Three integer dividers with fixed divider ratios (see Table 3)
— One fractional output divider
▪ Programmable loop bandwidth settings from 0.2Hz to 6.4kHz
— Optional fast-lock function
The PLL has a register-selectable loop bandwidth from 0.2Hz to
6.4kHz.
▪ Four General Purpose I/O pins with optional support for status
and control:
The device supports Output Enable and Clock Select inputs and
Lock, Holdover, and LOS status outputs.
— Two Output Enable control inputs provide control over the
four clocks
The device is programmable through an I2C interface. It also
supports I2C master capability to allow the register configuration
to be read from an external EEPROM.
— Manual clock selection control input
— Lock, Holdover, and Loss-of-Signal alarm outputs
▪ Open-drain Interrupt pin
Factory pre-programmed devices are also available using the
on-chip One Time Programmable (OTP) memory.
▪ Register programmable through I2C or via external I2C
EEPROM
▪ Full 2.5V or 3.3V supply modes, with some support for 1.8V
▪ -40°C to 85°C ambient operating temperature
Typical Applications
▪ OTN, including ITU-T G.709 (2009) FEC
▪ Package: 6 x 6 x 0.9 mm 40-VFQFN, lead-free (RoHS 6)
▪ CPRI interfaces
▪ Fiber optics
▪ 40G/100G Ethernet
▪ Gb Ethernet, Terabit IP switches / routers
©2018 Integrated Device Technology, Inc.
1
July 30, 2018
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