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8T49N234NLGI8 PDF预览

8T49N234NLGI8

更新时间: 2024-01-15 23:16:58
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
62页 1253K
描述
FemtoClock NG Universal Frequency Translator

8T49N234NLGI8 数据手册

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®
FemtoClock NG  
8T49N234  
Datasheet  
Universal Frequency Translator  
CISCO ONLY  
Description  
Features  
Supports SDH/SONET and Synchronous Ethernet clocks  
The 8T49N234 has one fractional-feedback PLL that can be used as  
a jitter attenuator and frequency translator. It is equipped with one  
integer and one fractional output divider, allowing the generation of  
up to two different output frequencies, ranging from 8kHz to 1GHz.  
These frequencies are completely independent of each other, the  
input reference frequencies and the crystal reference frequency. The  
device places virtually no constraints on input to output frequency  
conversion, supporting all FEC rates, including the new revision of  
ITU-T Recommendation G.709 (2009), most with 0ppm conversion  
error. The outputs may select among LVPECL, LVDS, HCSL or  
LVCMOS output levels.  
including all FEC rate conversions  
480fs RMS typical jitter (including spurs): 12kHz to 5MHz  
Operating modes: synthesizer, jitter attenuator  
Operates from a 10MHz to 50MHz fundamental-mode crystal or a  
10MHz to 125MHz external oscillator  
Accepts one LVPECL, LVDS, LVHSTL or LVCMOS input clock  
— Accepts frequencies ranging from 8kHz to 875MHz  
— Clock input monitoring  
Generates two LVPECL / LVDS / HCSL or four LVCMOS device  
outputs  
This makes it ideal to be used in any frequency synthesis  
application, including 1G, 10G, 40G and 100G Synchronous  
Ethernet, OTN, and SONET/SDH, including ITU-T G.709 (2009) FEC  
rates.  
— Output frequencies ranging from 8kHz up to 1.0GHz  
(differential)  
— Output frequencies ranging from 8kHz to 250MHz (LVCMOS)  
— One integer divider ranging from ÷4 to ÷786,420  
— Three fractional output dividers (see Output Dividers)  
Programmable loop bandwidth settings from 0.2Hz to 6.4kHz  
— Optional fast-lock function  
The 8T49N234 accepts one differential or single-ended input clock  
and a fundamental-mode crystal input. The internal PLL can lock to  
the input reference clock or just to the crystal to behave as a  
frequency synthesizer. A second input reference (FBIN) is used as  
the external feedback input for zero delay buffer functionality.  
Four general purpose I/O pins with optional support for status &  
The device monitors both input references for Loss-of-Signal (LOS),  
and generates an alarm when an input reference failure is detected.  
control:  
— Two output enable control inputs provide control over the  
device outputs  
The PLL has a register-selectable loop bandwidth from 0.2Hz to  
6.4kHz. The device starts up with output Q0 set to 12MHz, and  
output Q1 set to 6MHz. Loop bandwidth is set to 25Hz. Input clock,  
CLK is set to 6MHz.  
— Lock and Loss-of-Signal alarm outputs  
Open-drain Interrupt pin  
Register programmable through I2C  
The device supports output enable, inputs and Lock and LOS status  
outputs.  
The device is programmable through an I2C interface.  
Full 2.5V or 3.3V supply modes, 1.8V support for LVCMOS  
outputs, GPIO and control pins  
-40°C to 85°C ambient operating temperature  
Package: 40QFN, lead-free (RoHS 6)  
Typical Applications  
OTN or SONET / SDH equipment  
Gigabit and Terabit IP switches / routers including Synchronous  
Ethernet  
Video broadcast  
©2016 Integrated Device Technology, Inc  
1
December 13, 2016  
CONFIDENTIAL ONLY  

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