89HPES16T7
Product Brief
16-Lane 7-Port
PCI Express® Switch
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Legacy Support
– PCI compatible INTx emulation
– Bus locking
Highly Integrated Solution
– Requires no external components
Device Overview
The 89HPES16T7 is a member of the IDT PRECISE™ family of PCI
Express switching solutions. The PES16T7 is a 16-lane, 7-port periph-
eral chip that performs PCI Express Packet switching with a feature set
optimized for high performance applications such as servers, storage
and communications/networking. It provides connectivity and switching
functions between a PCI Express upstream port and up to seven down-
stream ports and supports switching between downstream ports.
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– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates sixteen 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
– Supports ECRC and Advanced Error Reporting
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC and
server motherboards
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Features
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High Performance PCI Express Switch
– Sixteen 2.5 Gbps PCI Express lanes
– Seven switch ports
– Upstream port configurable up to x8
– Two downstream ports configurable up to x4, four downstream
ports are x1
– Low-latency cut-through switch architecture
– Support for Max Payload Sizes up to 2048 bytes
– One virtual channel
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Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Eight traffic classes
– Supports PCI Power Management Interface specification (PCI-
– PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
PM 1.1)
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• Supports device power management states: D0, D3hot and
D3cold
– Automatic per port link width negotiation to x8, x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Unused SerDes are disabled
– Ability to load device configuration from serial EEPROM
Block Diagram
7-Port Switch Core / 16 PCI Express Lanes
Port
Frame Buffer
Route Table
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Transaction Layer
Transaction Layer
Data Link Layer
TL
TL
DLL
DLL
Data Link Layer
Multiplexer / Demultiplexer
Multiplexer / Demultiplexer
Multiplexer / Demultiplexer
Mux/Demux
Mux/Demux
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes SerDes
SerDes SerDes SerDes
SerDes SerDes SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
(Port 1)
(Port 6)
(Port 0)
(Port 2)
(Port 3)
Figure 1 Internal Block Diagram
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February 8, 2007
© 2007 Integrated Device Technology, Inc.