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89HPES16T7ZBBXG

更新时间： 2024-02-28 10:13:42
品牌 Logo 应用领域
艾迪悌 - IDT 时钟PC外围集成电路
页数 文件大小 规格书
31页 528K
描述
PCI Bus Controller, PBGA320, 25 X 25 MM, 1 MM PITCH, GREEN, BGA-320

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89HPES16T7ZBBXG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：LBGA,针数：320
Reach Compliance Code：compliantECCN代码：3A001.A.3
HTS代码：8542.31.00.01风险等级：5.29
其他特性：ALSO REQUIRES 3.3V SUPPLY地址总线宽度：
总线兼容性：PCI最大时钟频率：125 MHz
外部数据总线宽度：JESD-30 代码：R-PBGA-B320
JESD-609代码：e1长度：25 mm
湿度敏感等级：3端子数量：320
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.7 mm最大供电电压：1.1 V
最小供电电压：0.9 V标称供电电压：1 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：25 mmuPs/uCs/外围集成电路类型：BUS CONTROLLER, PCI
Base Number Matches：1

89HPES16T7ZBBXG 数据手册

 浏览型号89HPES16T7ZBBXG的Datasheet PDF文件第2页浏览型号89HPES16T7ZBBXG的Datasheet PDF文件第3页浏览型号89HPES16T7ZBBXG的Datasheet PDF文件第4页浏览型号89HPES16T7ZBBXG的Datasheet PDF文件第5页浏览型号89HPES16T7ZBBXG的Datasheet PDF文件第6页浏览型号89HPES16T7ZBBXG的Datasheet PDF文件第7页 
89HPES16T7  
Data Sheet  
Preliminary Information*  
16-Lane 7-Port PCI  
Express® Switch  
◆
◆
Legacy Support  
– PCI compatible INTx emulation  
– Bus locking  
Highly Integrated Solution  
– Requires no external components  
Device Overview  
The 89HPES16T7 is a member of IDT’s PRECISE™ family of PCI  
Express switching solutions. The PES16T7 is a 16-lane, 7-port periph-  
eral chip that performs PCI Express Packet switching with a feature set  
optimized for high performance applications such as servers, storage  
and communications/networking. It provides connectivity and switching  
functions between a PCI Express upstream port and up to six down-  
stream ports and supports switching between downstream ports.  
– Incorporates on-chip internal memory for packet buffering and  
queueing  
– Integrates sixteen 2.5 Gbps embedded SerDes with 8B/10B  
encoder/decoder (no separate transceivers needed)  
Reliability, Availability, and Serviceability (RAS) Features  
– Supports ECRC and Advanced Error Reporting  
– Internal end-to-end parity protection on all TLPs ensures data  
integrity even in systems that do not implement end-to-end  
CRC (ECRC)  
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O  
– Compatible with Hot-Plug I/O expanders used on PC and  
server motherboards  
◆
Features  
◆
High Performance PCI Express Switch  
– Sixteen 2.5 Gbps PCI Express lanes  
– Seven switch ports  
– Upstream port configurable up to x8  
– Two downstream ports configurable up to x4, four downstream  
ports are x1  
– Low-latency cut-through switch architecture  
– Support for Max Payload Sizes up to 2048 bytes  
– One virtual channel  
◆
Power Management  
– Utilizes advanced low-power design techniques to achieve low  
typical power consumption  
– Eight traffic classes  
– Supports PCI Power Management Interface specification (PCI-  
– PCI Express Base Specification Revision 1.1 compliant  
Flexible Architecture with Numerous Configuration Options  
PM 1.1)  
◆
– Unused SerDes are disabled  
– Automatic per port link width negotiation to x8, x4, x2 or x1  
– Automatic lane reversal on all ports  
– Automatic polarity inversion on all lanes  
– Supports Advanced Configuration and Power Interface Speci-  
fication, Revision 2.0 (ACPI) supporting active link state  
– Ability to load device configuration from serial EEPROM  
Block Diagram  
7-Port Switch Core / 16 PCI Express Lanes  
Port  
Frame Buffer  
Route Table  
Arbitration  
Scheduler  
Transaction Layer  
Data Link Layer  
Transaction Layer  
Transaction Layer  
Data Link Layer  
TL  
TL  
DLL  
DLL  
Data Link Layer  
Multiplexer / Demultiplexer  
Multiplexer / Demultiplexer  
Mux/Demux  
Multiplexer / Demultiplexer  
Mux/Demux  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
SerDes SerDes  
SerDes SerDes SerDes  
SerDes  
SerDes  
SerDes  
SerDes SerDes  
SerDes  
SerDes  
SerDes  
SerDes  
(Port 1)  
(Port 5)  
(Port 0)  
(Port 6)  
Figure 1 Internal Block Diagram  
(Port 2)  
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.  
1 of 31  
December 21, 2006  
© 2006 Integrated Device Technology, Inc.  
*Notice: The information in this document is subject to change without notice  
1234567...31

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