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889833AKLFT PDF预览

889833AKLFT

更新时间: 2024-11-11 20:05:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
17页 365K
描述
Low Skew Clock Driver, 889833 Series, 4 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220, VFQFN-16

889833AKLFT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220, VFQFN-16
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.84
系列:889833输入调节:DIFFERENTIAL
JESD-30 代码:S-XQCC-N16JESD-609代码:e3
长度:3 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:16
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC16,.12SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:0.52 ns认证状态:Not Qualified
座面最大高度:1 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3 mm最小 fmax:2000 MHz
Base Number Matches:1

889833AKLFT 数据手册

 浏览型号889833AKLFT的Datasheet PDF文件第2页浏览型号889833AKLFT的Datasheet PDF文件第3页浏览型号889833AKLFT的Datasheet PDF文件第4页浏览型号889833AKLFT的Datasheet PDF文件第5页浏览型号889833AKLFT的Datasheet PDF文件第6页浏览型号889833AKLFT的Datasheet PDF文件第7页 
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS  
FANOUT BUFFER W/INTERNAL TERMINATION  
ICS889833  
GENERAL DESCRIPTION  
FEATURES  
The ICS889833 is a high speed 1-to-4 Differential-  
Four differential LVDS outputs  
ICS  
to-LVDS Fanout Buffer w/Internal Termination and  
is a member of the HiPerClockS™ family of high  
performance clock solutions from IDT. The  
ICS889833 is optimized for high speed and very  
IN, nIN input pair can accept the following differential input  
levels: LVPECL, LVDS, CML  
HiPerClockS™  
Output frequency: >2GHz  
low output skew, making it suitable for use in demanding  
applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet,  
and Fibre Channel. The internally terminated differential input  
and VREF_AC pin allow other differential signal families such as  
LVPECL, LVDS, and CML to be easily interfaced to the input  
with minimal use of external components. The device also has  
an output enable pin which may be useful for system test and  
debug purposes. The ICS889833 is packaged in a small 3mm  
x 3mm 16-pin VFQFN package which makes it ideal for use in  
space-constrained applications.  
Cycle-to-cycle jitter, RMS: 0.2ps (maximum)  
Additive phase jitter, RMS: 0.04ps (typical)  
Total jitter: 10ps (maximum)  
Output skew: 40ps (maximum)  
Part-to-part skew: 200ps (maximum)  
Propagation delay: 520ps (maximum)  
3.3V operating supply  
-40°C to 85°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
16 15 14 13  
Q0  
Q0  
1
2
12 IN  
nQ0  
nQ0  
11 VT  
Q1  
3
4
10 VREF_AC  
IN  
VT  
Q1  
nQ1  
9
nIN  
50Ω  
50Ω  
5
6
7
8
nQ1  
nIN  
Q2  
VREF_AC  
ICS889833  
nQ2  
16-Lead VFQFN  
EN  
D
Q
3mm x 3mm x 0.925mm package body  
Q3  
K Package  
Top View  
nQ3  
IDT/ ICSLVDS FANOUT BUFFER W/INTERNAL TERMINATION  
1
ICS889833AK REV. B SEPTEMBER 9, 2008  

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