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889871AK

更新时间: 2024-11-11 19:32:11
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
17页 657K
描述
Low Skew Clock Driver, PQCC16

889871AK 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.92JESD-30 代码:S-PQCC-N16
JESD-609代码:e0逻辑集成电路类型:LOW SKEW CLOCK DRIVER
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCN封装等效代码:LCC16,.12SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):225电源:2.5/3.3 V
Prop。Delay @ Nom-Sup:0.975 ns认证状态:Not Qualified
子类别:Clock Drivers表面贴装:YES
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
Base Number Matches:1

889871AK 数据手册

 浏览型号889871AK的Datasheet PDF文件第2页浏览型号889871AK的Datasheet PDF文件第3页浏览型号889871AK的Datasheet PDF文件第4页浏览型号889871AK的Datasheet PDF文件第5页浏览型号889871AK的Datasheet PDF文件第6页浏览型号889871AK的Datasheet PDF文件第7页 
DIFFERENTIAL-TO-3.3V, 2.5V LVPECL BUFFER/  
DIVIDER W/INTERNAL TERMINATION  
ICS889871  
GENERAL DESCRIPTION  
FEATURES  
The ICS889871 is a high speed Differential-to-  
Three LVPECL outputs  
ICS  
3.3V, 2.5V LVPECL Buffer/Divider w/Internal  
Termination and is a member of the HiPerClockS™  
family of high performance clock solutions from  
IDT. The ICS889871 has a selectable ÷2, ÷4,  
Frequency divide select options: ÷2, ÷4, ÷8, ÷16  
HiPerClockS™  
IN, nIN input can accept the following differential input levels:  
LVPECL, LVDS, CML  
÷8, ÷16 output dividers. The clock input has internal  
termination resistors, allowing it to interface with several  
differential signal types while minimizing the number of  
required external components. The device is packaged in a  
small, 3mm x 3mm VFQFN package, making it ideal for use  
on space-constrained boards.  
Output frequency: 2GHz (typical)  
Additive phase jitter, RMS: 0.26ps (typical)  
Output skew: 7ps (typical), QB outputs  
Part-to-part skew: 250ps (maximum)  
Propagation Delay: 535ps (typical), QA/nQA outputs  
Supply voltage range: (LVPECL), 2.375V to 3.465V  
Supply voltage range: (ECL), -3.465V to -2.375V  
-40°C to 85°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
compliant packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
16 15 14 13  
QA  
QB0  
IN  
VT  
1
2
3
4
12  
nQA  
nQB0  
11  
VREF_AC  
QB1  
VREF_AC  
10  
9
nQB1  
nIN  
5
6
7
8
QB0  
IN  
50  
nQB0  
÷2, ÷4,  
÷8, ÷16  
VT  
nIN  
S0  
50Ω  
QB1  
Pullup  
Pullup  
ICS889871  
nBQ1  
16-Lead VFQFN  
Decoder  
S1  
3mm x 3mm x 0.95 package body  
K Package  
Top View  
Pullup  
nRESET  
IDT/ ICSLVPECL BUFFER/DIVIDER W/INTERNAL TERMINATION  
1
ICS889871AK REV A JULY 28, 2006  

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