Low Skew, 1-to-12 (IDCS)
879893
Datasheet
LVCMOS/LVTTL Clock Generator
General Description
Features
• Twelve LVCMOS/LVTTL outputs (two banks of six outputs);
The 879893 is a PLL clock driver designed specifically for redun-
dant clock tree designs. The device receives two LVCMOS/LVTTL
clock signals from which it generates 12 new LVCMOS/LVTTL
clock outputs. External PLL feedback is used to also provide zero
delay buffer performance.
One QFB feedback clock output
• Selectable CLK0 or CLK1 LVCMOS/LVTTL clock inputs
• CLK0, CLK1 supports the following input types:
LVCMOS, LVTTL
• Automatically detects clock failure
• IDCS on-chip intelligent dynamic clock switch
• Maximum output frequency: 200MHz
• Output skew: 50ps (maximum), within bank
• Cycle-to-cycle (FSEL3=0, VDD=3.3V±5%): 150ps (maximum)
• Smooth output phase transition during clock fail-over switch
• Full 3.3V or 2.5V supply modes
The 879893 Intelligent Dynamic Clock Switch (IDCS) circuit
continuously monitors both input CLK signals. Upon detection of a
failure (CLK stuck HIGH or LOW for at least 1 period), the
nALARM for that CLK will be latched (LOW). If that CLK is the
primary clock, the IDCS will switch to the good secondary clock
and phase/frequency alignment will occur with minimal output
phase disturbance.
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• For functional replacement part use 87973i
Pin Assignment
Simplified Block Diagram
Pulldown
nOE/MR
FSEL0 FSEL1 FSEL2 QA
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷2
÷2
÷2
÷4
÷2
÷16
÷8
÷4
1
0
Pulldown
Pulldown
0
1
CLK0
CLK1
6
REF
36 35 34 33 32 31 30 29 28 27 26 25
QA0:QA5
D
Q
PLL
GND
GND
QB0
QB1
VDD
37
38
39
40
24
23
22
21
VCO RANGE
240MHz - 500MHz
QA0
QA1
VDD
FB
FB
0
1
Pulldown
Pullup
6
REF_SEL
nMAN/A
nALARM_RST
IDCS
D
Q
QB0:QB5
QFB
GND
QA2
QA3
41
42
43
44
45
46
20 GND
÷2
Pullup
QB2
QB3
VDD
19
18
17
16
15
14
13
FSEL0 FSEL1 FSEL2 QB
Pulldown
nPLL_EN
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷16
÷8
VDD
GND
QA4
÷6
GND
QB4
QB5
VDD
÷8
D
Q
÷4
÷16
÷8
QA5 47
VDD
÷4
48
Pulldown
Pulldown
1 2 3 4 5 6 7 8 9 10 11 12
FSEL[0:2]
FSEL3
nALARM0
nALARM1
CLK_IND
879893
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2017 Integrated Device Technology, Inc.
1
Revision B, January 10, 2017