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879893AYILF PDF预览

879893AYILF

更新时间: 2024-11-06 01:12:07
品牌 Logo 应用领域
艾迪悌 - IDT DCS驱动分布式控制系统逻辑集成电路
页数 文件大小 规格书
16页 205K
描述
Low Skew, 1-to-12 (IDCS) LVCMOS/LVTTL Clock Generator

879893AYILF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:LQFP-48针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.37
其他特性:ALSO OPERATES AT 3.3V SUPPLY系列:879893
输入调节:MUXJESD-30 代码:S-PQFP-G48
JESD-609代码:e3长度:7 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.024 A
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:48
实输出次数:12最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP48,.35SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:2.5/3.3 VProp。Delay @ Nom-Sup:0.13 ns
传播延迟(tpd):0.13 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
最小 fmax:200 MHzBase Number Matches:1

879893AYILF 数据手册

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Low Skew, 1-to-12 (IDCS)  
879893  
Datasheet  
LVCMOS/LVTTL Clock Generator  
General Description  
Features  
Twelve LVCMOS/LVTTL outputs (two banks of six outputs);  
The 879893 is a PLL clock driver designed specifically for redun-  
dant clock tree designs. The device receives two LVCMOS/LVTTL  
clock signals from which it generates 12 new LVCMOS/LVTTL  
clock outputs. External PLL feedback is used to also provide zero  
delay buffer performance.  
One QFB feedback clock output  
Selectable CLK0 or CLK1 LVCMOS/LVTTL clock inputs  
CLK0, CLK1 supports the following input types:  
LVCMOS, LVTTL  
Automatically detects clock failure  
IDCS on-chip intelligent dynamic clock switch  
Maximum output frequency: 200MHz  
Output skew: 50ps (maximum), within bank  
Cycle-to-cycle (FSEL3=0, VDD=3.3V±5%): 150ps (maximum)  
Smooth output phase transition during clock fail-over switch  
Full 3.3V or 2.5V supply modes  
The 879893 Intelligent Dynamic Clock Switch (IDCS) circuit  
continuously monitors both input CLK signals. Upon detection of a  
failure (CLK stuck HIGH or LOW for at least 1 period), the  
nALARM for that CLK will be latched (LOW). If that CLK is the  
primary clock, the IDCS will switch to the good secondary clock  
and phase/frequency alignment will occur with minimal output  
phase disturbance.  
-40°C to 85°C ambient operating temperature  
Available in lead-free (RoHS 6) package  
For functional replacement part use 87973i  
Pin Assignment  
Simplified Block Diagram  
Pulldown  
nOE/MR  
FSEL0 FSEL1 FSEL2 QA  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷2  
÷2  
÷2  
÷4  
÷2  
÷16  
÷8  
÷4  
1
0
Pulldown  
Pulldown  
0
1
CLK0  
CLK1  
6
REF  
36 35 34 33 32 31 30 29 28 27 26 25  
QA0:QA5  
D
Q
PLL  
GND  
GND  
QB0  
QB1  
VDD  
37  
38  
39  
40  
24  
23  
22  
21  
VCO RANGE  
240MHz - 500MHz  
QA0  
QA1  
VDD  
FB  
FB  
0
1
Pulldown  
Pullup  
6
REF_SEL  
nMAN/A  
nALARM_RST  
IDCS  
D
Q
QB0:QB5  
QFB  
GND  
QA2  
QA3  
41  
42  
43  
44  
45  
46  
20 GND  
÷2  
Pullup  
QB2  
QB3  
VDD  
19  
18  
17  
16  
15  
14  
13  
FSEL0 FSEL1 FSEL2 QB  
Pulldown  
nPLL_EN  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷16  
÷8  
VDD  
GND  
QA4  
÷6  
GND  
QB4  
QB5  
VDD  
÷8  
D
Q
÷4  
÷16  
÷8  
QA5 47  
VDD  
÷4  
48  
Pulldown  
Pulldown  
1 2 3 4 5 6 7 8 9 10 11 12  
FSEL[0:2]  
FSEL3  
nALARM0  
nALARM1  
CLK_IND  
879893  
48-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y Package  
Top View  
©2017 Integrated Device Technology, Inc.  
1
Revision B, January 10, 2017  

879893AYILF 替代型号

型号 品牌 替代类型 描述 数据表
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完全替代

Low Skew, 1-to-12 (IDCS) LVCMOS/LVTTL Clock Generator

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