Datasheet > 879S216AKI-02LFT

879S216AKI-02LFT

更新时间： 2024-09-18 01:16:59

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
22页	873K
描述
2:2, Differential-to-LVPECL/LVDS Divider

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879S216AKI-02LFT 数据手册

2:2, Differential-to-LVPECL/LVDS Divider ICS879S216I-02

DATA SHEET

General Description

Features

The ICS879S216I-02 is a Differential-to-LVPECL/ LVDS Clock

Divider which can operate up to 2.5GHz. ICS879S216I-02 has 2

selectable differential clock inputs. The fully differential architecture

and low propagation delay make it ideal for use in clock distribution

circuits. ICS879S216I-02 can divide the input clock by ÷2, ÷4, ÷8

and ÷16. Table 4A lists all the available output dividers.

• High speed 2:2 differential divider

• Two differential LVPECL or LVDS output pairs

• Four selectable divide combinations

• PCLKx can accept the following input levels: LVPECL, LVDS, CML

• Maximum input frequency: 2.5GHz

• Propagation delay: 0.8ns (minimum), 1.6ns (maximum)

• Output Skew: 25ps (maximum)

• Full 3.3V or 2.5V supply modes

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 5) package

Table 1A. V_{CC_TAP}Function Table

Outputs

Q[1:0], nQ[1:0]

LVPECL

LVDS

Output Level Supply

V_{CC_TAP}

V_CC

Table 1B. SEL_OUT Function Table

2.5V

3.3V

2.5V

3.3V

Input

Outputs

Q[1:0], nQ[1:0]

LVPECL (default)

LVDS

V_CC

SEL_OUT

V_CC

LVDS

Float

Pin Assignment

Block Diagram

Pullup

SEL_OUT

24 23 22 21 20 19

Pulldown

CLK_SEL

V^CC

PCLK0

nPCLK0

PCLK1

Pulldown

PCLK0

16 nc

15 nc

Pullup/Pulldown

nPCLK0

nPCLK1

SEL_OUT

nQ0

00 ÷2,

01 ÷4,

10 ÷8,

V^EE

9 10 11 12

Pulldown

PCLK1

11 ÷16 ^(default)

nQ1

Pullup/Pulldown

nPCLK1

ICS879S216I-02

24-Lead VFQFN

4mm x 4mm x 0.95mm package body

Pullup

F_SEL[1:0]

K Package

Top View

ICS879S216AKI-02 REVISION A APRIL 8, 2011

12 3 4 5 6 7...22

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