ICS87972I-147
LOW SKEW, 1-TO-12
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS87972I-147 is a low skew, LVCMOS/LVTTL
• Fully integrated PLL
ICS
Clock Generator and a member of the HiPerClockS™
• 14 LVCMOS/LVTTL outputs; (12)clocks, (1)feedback, (1)sync
HiPerClockS™
family of High Performance Clock Solutions from
ICS.The ICS87972I-147 has three selectable inputs
and provides 14 LVCMOS/LVTTL outputs.
• Selectable crystal oscillator interface or LVCMOS/LVTTL
reference clock inputs
• CLK0, CLK1 can accept the following input levels:
The ICS87972I-147 is a highly flexible device. Using the crystal
oscillator input, it can be used to generate clocks for a system.
All of these clocks can be the same frequency or the device can
be configured to generate up to three different frequencies among
the three output banks. Using one of the single ended inputs, the
ICS87972I-147 can be used as a zero delay buffer/multiplier/
divider in clock distribution applications.
LVCMOS or LVTTL
• Output frequency range: 10MHz to 150MHz
• VCO range: 240MHz to 500MHz
• Output skew: 200ps (maximum)
• Cycle-to-cycle jitter, (all banks ÷4): 55ps (maximum)
• Full 3.3V operating supply
The three output banks and feedback output each have their
own output dividers which allows the device to generate a
multitude of different bank frequency ratios and output-to-input
frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3)
can be selected to be inverting or non-inverting. The output
frequency range is 10MHz to 150MHz. Input frequency range is
6MHz to 150MHz.
• -40°C to 85°C ambient operating temperature
• Pin compatible with MPC972
• Compatible with PowerPC™andPentium™ Microprocessors
The ICS87972I-147 also has a QSYNC output which can be
used or system synchronization purposes. It monitors Bank A
and Bank C outputs and goes low one period of the faster clock
prior to coincident rising edges of Bank A and Bank C clocks.
QSYNC then goes high again when the coincident rising edges
of Bank A and Bank C occur. This feature is used primarily in
applications where Bank A and Bank C are running at different
frequencies, and is particularly useful when they are running at
non-integer multiples of one another.
PIN ASSIGNMENT
39 38 37 36 35 34 33 32 31 30 29 28 27
FSEL_B1
FSEL_B0
FSEL_A1
FSEL_A0
QA3
40
41
42
43
44
45
46
47
48
49
50
51
52
26
25
24
23
22
21
20
19
18
17
16
15
14
FSEL_FB1
QSYNC
GNDO
QC0
Example Applications:
1. System Clock generator: Use a 16.66 MHz Crystal to
generate eight 33.33MHz copies for PCI and four 100MHz
copies for the CPU or PCI-X.
VDDO
VDDO
QC1
QA2
FSEL_C0
FSEL_C1
QC2
ICS87972I-147
2. Line Card Multiplier: Multiply 19.44MHz from a back plane
to 77.76MHz for the line Card ASICs and Serdes.
GNDO
QA1
3. Zero Delay buffer for Synchronous memory: Fan out up
to twelve 100MHz copies from a memory controller ref-
erence clock to the memory chips on a memory module
with zero delay.
VDDO
VDDO
QA0
QC3
GNDO
VCO_SEL
GNDO
INV_CLK
1
2
3
4
5
6
7
8
9 10 11 12 13
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
TopView
87972DYI-147
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 24, 2009
1