87973DYI-147

更新时间： 2024-11-05 06:33:31

品牌	Logo	应用领域
艾迪悌 - IDT		时钟
页数	文件大小	规格书
19页	1156K
描述
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

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87973DYI-147 数据手册

LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/

ZERO DELAY BUFFER

ICS87973I-147

General Description

Features

The ICS87973I-147 is a LVCMOS/LVTTL clock

• Fully integrated PLL

generator and a member of the HiPerClockS™family

of High Performance Clock Solutions from IDT. The

ICS87973I-147 has three selectable inputs and

provides 14 LVCMOS/LVTTL outputs.

• Fourteen LVCMOS/LVTTL outputs to include: twelve clocks,

HiPerClockS™

one feedback, one sync

• Selectable differential CLK, nCLK inputs or LVCMOS/LVTTL

reference clock inputs

The ICS87973I-147 is a highly flexible device. The three

selectable inputs (1 differential and 2 single ended inputs) are

often used in systems requiring redundant clock sources. Up to

three different output frequencies can be generated among the

three output banks.

• CLK0, CLK1 can accept the following input levels:

LVCMOS or LVTTL

• CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Output frequency range: 10MHz to 150MHz

• VCO range: 240MHz to 500MHz

The three output banks and feedback output each have their own

output dividers which allows the device to generate a multitude of

different bank frequency ratios and output-to-input frequency

ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be

selected to be inverting or non-inverting. The output frequency

range is 10MHz to 150MHz. The input frequency range is 6MHz to

120MHz.

• Output skew: 200ps (maximum)

• Cycle-to-cycle jitter, (all banks ÷4): 55ps (maximum)

• Full 3.3V supply voltage

• -40°C to 85°C ambient operating temperature

• Compatible with PowerPC™and Pentium™Microprocessors

The ICS87973I-147 also has a QSYNC output which can be used

for system synchronization purposes. It monitors Bank A and

Bank C outputs and goes low one period prior to coincident rising

edges of Bank A and Bank C clocks. QSYNC then goes high again

when the coincident rising edges of Bank A and Bank C occur.

This feature is used primarily in applications where Bank A and

Bank C are running at different frequencies, and is particularly

useful when they are running at non-integer multiples of one

another.

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

Pin Assignment

Example Applications:

39 38 37 36 35 34 33 32 31 30 29 28 27

1.System Clock generator: Use a 16.66MHz reference clock to

generate eight 33.33MHz copies for PCI and four 100MHz

copies for the CPU or PCI-X.

FSEL_B1 40

FSEL_B0 41

FSEL_A1 42

FSEL_FB1

QSYNC

24 GNDO

2.Line Card Multiplier: Multiply differential 62.5MHz from a back

plane to single-ended 125MHz for the line Card ASICs and

Gigabit Ethernet Serdes.

QC0

FSEL_A0

QA3

22 V_DDO

21 QC1

V_DDO

QA2

20 FSEL_C0

3.Zero Delay buffer for Synchronous memory: Fanout up to twelve

100MHz copies from a memory controller reference clock to the

memory chips on a memory module with zero delay.

GNDO 47

QA1 48

FSEL_C1

QC2

V_DDO

QA0 50

QC3

15 GNDO

GNDO

VCO_SEL

14 INV_CLK

2 3 4 5 6 7 8 9 10 11 12 13

ICS87973I-147

52-Lead LQFP

10mm x 10mm x 1.4mm package body

Y Package

Top View

IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

ICS87973DYI-147 REV. A DECEMBER 9, 2008

12 3 4 5 6 7...19

中文翻译

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87973DYI-147 替代型号

型号	品牌	替代类型	描述	数据表
87973DYIT	IDT	完全替代	PLL Based Clock Driver, 87973 Series, 13 True Output(s), 0 Inverted Output(s), CMOS, PQFP5
87973DYI	IDT	完全替代	PLL Based Clock Driver, 87973 Series, 13 True Output(s), 0 Inverted Output(s), CMOS, PQFP5
ICS87973DYILF	IDT	功能相似	PLL Based Clock Driver, 13 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40

与87973DYI-147相关器件

型号	品牌	获取价格	描述	数据表
87973DYI-147LF	IDT	获取价格	LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
87973DYI-147LFT	IDT	获取价格	LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
87973DYI-147T	IDT	获取价格	LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
87973DYILF	IDT	获取价格	Low Skew, 1-to-12 LVCMOS / LVTTL Clock Mult iplier/Zero Delay Buffer
87973DYILFT	IDT	获取价格	Low Skew, 1-to-12 LVCMOS / LVTTL Clock Mult iplier/Zero Delay Buffer
87973DYIT	IDT	获取价格	PLL Based Clock Driver, 87973 Series, 13 True Output(s), 0 Inverted Output(s), CMOS, PQFP5
87973I-147	IDT	获取价格	Low Skew, 1-to-12 LVCMOS/ LVTTL Clock Multiplier/ Zero Delay Buffer
87973I-147_16	IDT	获取价格	Low Skew, 1-to-12 LVCMOS/ LVTTL Clock Multiplier/ Zero Delay Buffer
87974CYI	IDT	获取价格	PLL Based Clock Driver, 87974 Series, 15 True Output(s), 0 Inverted Output(s), PQFP52, 10
87974CYILF	IDT	获取价格	Low Skew, 1-to-15, LVCMOS/LVTTL Clock Generator

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