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85408_15 PDF预览

85408_15

更新时间: 2024-01-24 01:14:58
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
16页 299K
描述
Low Skew, 1-to-8, Differential-to-LVDS Clock

85408_15 数据手册

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Low Skew, 1-to-8, Differential-to-LVDS  
Clock  
85408  
DATA SHEET  
General Description  
Features  
The 85408 is a low skew, high performance 1-to-8  
Eight differential LVDS output pairs  
Differential-to-LVDS Clock Distribution Chip. The 85408 CLK, nCLK  
pair can accept most differential input levels and translates them to  
3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling  
(LVDS), the 85408 provides a low power, low noise, low skew,  
point-to-point solution for distributing LVDS clock signals.  
CLK/nCLK can accept the following differential input levels:  
LVPECL, LVDS, LVHSTL, HCSL, SSTL  
Maximum output frequency: 700MHz  
Translates any differential input signal (LVPECL, LVHSTL, SSTL,  
HCSL) to LVDS levels without external bias networks  
Guaranteed output and part-to-part skew specifications make the  
85408 ideal for those applications demanding well defined  
performance and repeatability.  
Translates any single-ended input signal to LVDS with resistor  
bias on nCLK input  
Output skew: 50ps (maximum)  
Part-to-part skew: 550ps (maximum)  
Propagation delay: 2.4ns (maximum)  
3.3V operating supply  
0°C to 70°C ambient operating temperature  
Available in lead-free (RoHS 6) package  
Block Diagram  
Pin Assignment  
OE  
Q7  
1
2
24  
23  
nQ6  
Q6  
nQ7  
OE  
Q0  
nQ5  
Q5  
3
4
22  
21  
nQ0  
GND  
Q1  
5
6
7
20  
19  
18  
17  
V
DD  
DD  
nQ4  
Q4  
nQ3  
nQ1  
V
GND  
Q2  
Q3  
8
V
DD  
nQ2  
9
nQ2  
Q2  
16  
15  
14  
13  
CLK  
nCLK  
Q0  
Q3  
10  
11  
12  
nQ3  
CLK  
nCLK  
nQ1  
Q1  
Q4  
nQ0  
nQ4  
85408  
Q5  
nQ5  
24-Lead TSSOP  
4.4mm x 7.8mm x 0.925mm package body  
G Package  
Q6  
nQ6  
Q7  
Top View  
nQ7  
85408 Rev C 1/5/15  
1
©2015 Integrated Device Technology, Inc.  

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