Datasheet > 85408BGT

85408BGT

更新时间： 2024-09-25 04:52:43

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
16页	756K
描述
Low Skew Clock Driver, 85408 Series, 8 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.925 MM HEIGHT, MO-153, TSSOP-24

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85408BGT 数据手册

ICS85408

Low Skew, 1-to-8,

Differential-to-LVDS Clock

DATASHEET

General Description

Features

The ICS85408 is a low skew, high performance 1-to-8

Differential-to-LVDS Clock Distribution Chip and a

member of the HiPerClockS™ family of High

• Eight differential LVDS output pairs

• CLK/nCLK can accept the following differential input levels:

HiPerClockS™

LVPECL, LVDS, LVHSTL, HCSL, SSTL

Performance Clock Solutions from IDT. The ICS85408

CLK, nCLK pair can accept most differential input

levels and translates them to 3.3V LVDS output levels. Utilizing Low

Voltage Differential Signaling (LVDS), the ICS85408 provides a low

power, low noise, low skew, point-to-point solution for distributing

LVDS clock signals.

• Maximum output frequency: 700MHz

• Translates any differential input signal (LVPECL, LVHSTL, SSTL,

HCSL) to LVDS levels without external bias networks

• Translates any single-ended input signal to LVDS with resistor

bias on nCLK input

• Output skew: 50ps (maximum)

Guaranteed output and part-to-part skew specifications make the

ICS85408 ideal for those applications demanding well defined

performance and repeatability.

• Part-to-part skew: 550ps (maximum)

• Propagation delay: 2.4ns (maximum)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

Block Diagram

Pin Assignment

nQ7

nQ6

nQ0

nQ5

GND

nQ1

nQ4

nQ3

GND

nQ2

nQ1

CLK

nCLK

nQ3

CLK

nCLK

nQ0

nQ4

ICS85408

nQ5

24-Lead TSSOP

4.4mm x 7.8mm x 0.925mm package body

G Package

nQ6

nQ7

Top View

ICS85408BG REVISION B JUNE 25, 2009

12 3 4 5 6 7...16

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