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85408BG PDF预览

85408BG

更新时间: 2024-01-05 23:43:48
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 756K
描述
Low Skew Clock Driver, 85408 Series, 8 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.925 MM HEIGHT, MO-153, TSSOP-24

85408BG 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:4.40 X 7.80 MM, 0.925 MM HEIGHT, MO-153, TSSOP-24针数:24
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.21
系列:85408输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G24JESD-609代码:e0
长度:7.8 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:24
实输出次数:8最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP24,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):225
电源:3.3 VProp。Delay @ Nom-Sup:2.4 ns
传播延迟(tpd):2.4 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
最小 fmax:700 MHzBase Number Matches:1

85408BG 数据手册

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ICS85408  
Low Skew, 1-to-8,  
Differential-to-LVDS Clock  
DATASHEET  
General Description  
Features  
The ICS85408 is a low skew, high performance 1-to-8  
Differential-to-LVDS Clock Distribution Chip and a  
member of the HiPerClockS™ family of High  
Eight differential LVDS output pairs  
S
IC  
CLK/nCLK can accept the following differential input levels:  
HiPerClockS™  
LVPECL, LVDS, LVHSTL, HCSL, SSTL  
Performance Clock Solutions from IDT. The ICS85408  
CLK, nCLK pair can accept most differential input  
levels and translates them to 3.3V LVDS output levels. Utilizing Low  
Voltage Differential Signaling (LVDS), the ICS85408 provides a low  
power, low noise, low skew, point-to-point solution for distributing  
LVDS clock signals.  
Maximum output frequency: 700MHz  
Translates any differential input signal (LVPECL, LVHSTL, SSTL,  
HCSL) to LVDS levels without external bias networks  
Translates any single-ended input signal to LVDS with resistor  
bias on nCLK input  
Output skew: 50ps (maximum)  
Guaranteed output and part-to-part skew specifications make the  
ICS85408 ideal for those applications demanding well defined  
performance and repeatability.  
Part-to-part skew: 550ps (maximum)  
Propagation delay: 2.4ns (maximum)  
3.3V operating supply  
0°C to 70°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Block Diagram  
Pin Assignment  
OE  
Q7  
nQ7  
OE  
1
2
24  
23  
nQ6  
Q6  
Q0  
nQ0  
nQ5  
Q5  
3
4
22  
21  
GND  
Q1  
nQ1  
5
6
7
20  
19  
18  
17  
V
V
DD  
DD  
nQ4  
Q4  
nQ3  
GND  
Q2  
nQ2  
Q3  
8
V
DD  
9
nQ2  
Q2  
nQ1  
16  
15  
14  
13  
CLK  
nCLK  
Q0  
Q3  
nQ3  
10  
11  
12  
CLK  
nCLK  
Q4  
Q1  
nQ0  
nQ4  
ICS85408  
Q5  
nQ5  
24-Lead TSSOP  
4.4mm x 7.8mm x 0.925mm package body  
G Package  
Q6  
nQ6  
Q7  
nQ7  
Top View  
ICS85408BG REVISION B JUNE 25, 2009  
1
©2009 Integrated Device Technology, Inc.  

85408BG 替代型号

型号 品牌 替代类型 描述 数据表
85408BGLFT IDT

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Low Skew, 1-to-8, Differential-to-LVDS Clock
85408BGLF IDT

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85408BGILF IDT

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Low Skew, 1-to-8 , Different ial-to-LVDS Clock

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