Datasheet > 85408I

85408I

更新时间： 2024-09-25 01:13:35

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	299K
描述
Low Skew, 1-to-8 , Different ial-to-LVDS Clock

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85408I 数据手册

Low Skew , 1-to-8, Differential-to-LVDS Clock

85408I

Datasheet

General Description

Features

The 85408I is a low skew, high performance 1-to-8

• Eight differential LVDS output pairs

• One differential clock input pair

Differential-to-LVDS Clock Distribution Chip. The 85408I CLK, nCLK

pair can accept most differential input levels and translates them to

3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling

(LVDS), the 85408I provides a low power, low noise, low skew,

point-to-point solution for distributing LVDS clock signals.

• CLK, nCLK can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, HCSL, SSTL

• Maximum output frequency: 700MHz

• Translates any differential input signal (LVPECL, LVHSTL, SSTL,

HCSL) to LVDS levels without external bias networks

Guaranteed output and part-to-part skew specifications make the

85408I ideal for those applications demanding well defined

performance and repeatability.

• Translates any single-ended input signal to LVDS with resistor

bias on nCLK input

• Multiple output enable inputs for disabling unused outputs

in reduced fanout applications

• Additive phase jitter, RMS: 167fs (typical)

• Output skew: 50ps (maximum)

• Part-to-part skew: 550ps (maximum)

• Propagation delay: 2.4ns (maximum)

• 3.3V operating supply

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package

Block Diagram

Pin Assignment

nQ6

nQ7

nQ5

nQ0

GND

nQ4

nQ3

nQ1

GND

nQ2

CLK

nCLK

nQ3

CLK

nCLK

nQ1

nQ0

nQ4

85408I

nQ5

24-Lead TSSOP

4.4mm x 7.8mm x 0.925mm package body

G Package

nQ6

Top View

nQ7

Revision C, February 23, 2016

12 3 4 5 6 7...16

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