Datasheet > 8430DY-111

8430DY-111

更新时间： 2024-02-17 03:47:21

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
18页	172K
描述
Clock Driver, 8430 Series, 2 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32

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8430DY-111 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32	针数：	32
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.62
系列：	8430	输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e0
长度：	7 mm	逻辑集成电路类型：	CLOCK DRIVER
湿度敏感等级：	3	功能数量：	1
反相输出次数：		端子数量：	32
实输出次数：	2	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	峰值回流温度（摄氏度）：	240
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.015 ns
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	20	宽度：	7 mm
Base Number Matches：	1

8430DY-111 数据手册

700MHz, Low Jitter, Differential-to-

3.3V LVPECL Frequency Synthesizer

ICS8430-111

PRELIMINARY DATA SHEET

FUNCTIONAL DESCRIPTION

The M value and the required values of M0 through M8 are

shown in Table 3B, Programmable VCO Frequency Function

Table. Valid M values for which the PLL will achieve lock are

defined as 125 ≤ M ≤ 350. The frequency out is defined as

The ICS8430-111 features a fully integrated PLL and there-

fore requires no external components for setting the loop

bandwidth. A differential clock input is used as the input to the

on-chip oscillator. The output of the oscillator is divided by 16

prior to the phase detector. A16MHz clock input provides a

1MHz reference frequency. The VCO of the PLL operates over

a range of 200 to 700MHz. The output of the M divider is also

applied to the phase detector.

follows:

fVCO fxtal 2M

fout

Serial operation occurs when nP_LOAD is HIGH and S_LOAD

is LOW. The shift register is loaded by sampling the S_DATA

bits with the rising edge of S_CLOCK. The contents of the shift

S_LOAD transitions from LOW-to-HIGH. The M divide and N

output divide values are latched on the HIGH-to-LOW transi-

tion of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA

input is passed directly to the M divider and N output divider on

each rising edge of S_CLOCK. The serial mode can be used to

program the M and N bits and test bits T1 and T0. The internal

registers T0 and T1 determine the state of the TEST output as

follows:

The phase detector and the M divider force the VCO output

frequency to be 2M times the reference frequency by adjusting

the VCO control voltage. Note that for some values of M (either

too high or too low), the PLL will not achieve lock. The output

of the VCO is scaled by a divider prior to being sent to each of

the LVPECL output buffers. The divider provides a 50% output

duty cycle.

The programmable features of the ICS8430-111 support two

input modes to program the M divider and N output divider.

The two input operational modes are parallel and serial. Fig-

ure 1 shows the timing diagram for each mode. In parallel mode

the nP_LOAD input is LOW. The data on inputs M0 through

M8 and N0 through N1 is passed directly to the M divider and

N output divider. On the LOW-to-HIGH transition of the

nP_LOAD input, the data is latched and the M divider remains

loaded until the next LOW transition on nP_LOAD or until a

serial event occurs. The TEST output is Mode 000 (shift regis-

ter out) when operating in the parallel input mode. The rela-

tionship between the VCO frequency, the crystal frequency

T1 T0

TEST Output

LOW

S_Data, Shift Register Input

Output of M divider

CMOS Fout

and the M divider is defined as follows:

fxtal

fVCO =

SERIAL LOADING

S_CLOCK

S_DATA

S_LOAD

nP_LOAD

PARALLEL LOADING

M, N

M0:M8, N0:N1

nP_LOAD

S_LOAD

Time

FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS

*NOTE: The NULL timing slot must be observed.

ICS8430DY-111 REVISION F JUNE 22, 2009

123 4 5 6 7...18

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