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8430BYI-71LFT

更新时间： 2024-02-03 00:39:23
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路晶体
页数 文件大小 规格书
16页 167K
描述
Clock Generator, 700MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32

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8430BYI-71LFT 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：QFP
包装说明：7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32针数：32
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.18
Is Samacsys：NJESD-30 代码：S-PQFP-G32
JESD-609代码：e3长度：7 mm
湿度敏感等级：3端子数量：32
最高工作温度：85 °C最低工作温度：-40 °C
最大输出时钟频率：700 MHz封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE峰值回流温度（摄氏度）：260
主时钟/晶体标称频率：27 MHz认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：7 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHER
Base Number Matches：1

8430BYI-71LFT 数据手册

 浏览型号8430BYI-71LFT的Datasheet PDF文件第1页浏览型号8430BYI-71LFT的Datasheet PDF文件第2页浏览型号8430BYI-71LFT的Datasheet PDF文件第4页浏览型号8430BYI-71LFT的Datasheet PDF文件第5页浏览型号8430BYI-71LFT的Datasheet PDF文件第6页浏览型号8430BYI-71LFT的Datasheet PDF文件第7页 
PRELIMINARY  
ICS8430BI-71  
Integrated  
Circuit  
Systems, Inc.  
700MHZ, LOW JITTER, CRYSTAL INTERFACE/  
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER  
TABLE 1. PIN DESCRIPTIONS  
Number  
Name  
Type  
Pulldown  
Description  
1, 2, 3,  
28, 29, 30  
31, 32  
M5, M6, M7,  
M0, M1, M2,  
M3, M4  
Input  
M divider inputs. Data latched on LOW-to-HIGH transition of  
nP_LOAD input. LVCMOS / LVTTL interface levels.  
4
5, 6  
7
M8  
N0, N1  
N2  
Input  
Input  
Input  
Power  
Pullup  
Pulldown  
Pullup  
Determines output divider value as defined in Table 3C  
Function Table. LVCMOS / LVTTL interface levels.  
8, 16  
VEE  
Negative supply pins.  
Test output which is ACTIVE in the serial mode of operation.  
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.  
Core power supply pin.  
9
TEST  
VCC  
FOUT1,  
nFOUT1  
VCCO  
FOUT0,  
nFOUT0  
Output  
Power  
Output  
Power  
Output  
10  
11, 12  
13  
Differential output for the synthesizer. 3.3V LVPECL interface levels.  
Output supply pin.  
14, 15  
Differential output for the synthesizer. 3.3V LVPECL interface levels.  
Active High Master reset. When logic HIGH, the internal dividers are  
reset causing the true outputs (FOUTx) to go low and the inverted  
17  
MR  
Input  
Pulldown outputs (nFOUTx) to go high. When Logic LOW, the internal dividers  
and the outputs are enabled. Assertion of MR does not affect loaded  
M, N, and T values. LVCMOS / LVTTL interface levels.  
Clocks in serial data present at S_DATA input into the shift register  
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.  
Shift register serial input. Data sampled on the rising edge of  
S_CLOCK. LVCMOS / LVTTL interface levels.  
18  
19  
S_CLOCK  
S_DATA  
Input  
Input  
Pulldown  
Pulldown  
Controls transition of data from shift register into the dividers.  
LVCMOS / LVTTL interface levels.  
Analog supply pin.  
20  
21  
S_LOAD  
VCCA  
Input  
Pulldown  
Power  
Selects between the crystal oscillator or test clock as the  
22  
23  
24,  
25  
XTAL_SEL  
TEST_CLK  
XTAL_OUT,  
XTAL_IN  
Input  
Pullup  
PLL reference source. Selects XTAL inputs when HIGH.  
Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels.  
Input  
Input  
Pulldown Test clock input. LVCMOS interface levels.  
Crystal oscillator interface. XTAL_IN is the input.  
XTAL_OUT is the output.  
Parallel load input. Determines when data present at M8:M0 is  
Pulldown loaded into the M divider, and when data present at N2:N0 sets the  
N output divider value. LVCMOS / LVTTL interface levels.  
26  
nP_LOAD  
Input  
Determines whether synthesizer is in PLL or bypass mode.  
LVCMOS / LVTTL interface levels.  
27  
VCO_SEL  
Input  
Pullup  
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
TABLE 2. PIN CHARACTERISTICS  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum Typical Maximum Units  
Input Capacitance  
Input Pullup Resistor  
4
pF  
kΩ  
kΩ  
RPULLUP  
51  
51  
RPULLDOWN Input Pulldown Resistor  
8430BYI-71  
www.icst.com/products/hiperclocks.html  
REV.A FEBRUARY 17, 2006  
3
1234567...16

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