8302502RA

更新时间： 2024-11-20 11:47:47

品牌	Logo	应用领域
德州仪器 - TI		计数器触发器逻辑集成电路输出元件
页数	文件大小	规格书
20页	608K
描述
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS WITH 3-STATE OUTPUTS

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技术参数
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8302502RA 技术参数

生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP, DIP20,.3	针数：	20
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
Factory Lead Time：	1 week	风险等级：	1.51
其他特性：	TCO OUTPUT; CLOCKED CARRY OUTPUT	计数方向：	BIDIRECTIONAL
系列：	ALS	JESD-30 代码：	R-GDIP-T20
长度：	24.2 mm	负载电容（CL）：	50 pF
负载/预设输入：	YES	逻辑集成电路类型：	BINARY COUNTER
最大I（ol）：	0.024 A	工作模式：	SYNCHRONOUS
位数：	4	功能数量：	1
端子数量：	20	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出特性：	3-STATE
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DIP
封装等效代码：	DIP20,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	包装方法：	TUBE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
最大电源电流（ICC）：	32 mA	Prop。Delay @ Nom-Sup：	28 ns
传播延迟（tpd）：	21 ns	认证状态：	Qualified
筛选级别：	MIL-STD-883	座面最大高度：	5.08 mm
子类别：	Counter	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	TTL
温度等级：	MILITARY	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	触发器类型：	POSITIVE EDGE
宽度：	6.92 mm	最小 fmax：	25 MHz
Base Number Matches：	1

8302502RA 数据手册

SN54ALS569A, SN74ALS568A, SN74ALS569A

SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS

WITH 3-STATE OUTPUTS

SDAS229A – APRIL 1982 – REVISED JANUARY 1995

SN54ALS569A . . . J PACKAGE

SN74ALS568A, SN74ALS569A . . . DW OR N PACKAGE

(TOP VIEW)

• 3-State Q Outputs Drive Bus Lines Directly

• Counter Operation Independent of 3-State

Output

• Fully Synchronous Clear, Count, and Load

• Asynchronous Clear Is Also Provided

• Fully Cascadable

• Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), and Standard Plastic (N)

and Ceramic (J) 300-mil DIPs

U/D

CLK

RCO

CCO

ENP

ACLR

SCLR

GND

12 ENT

description

LOAD

The SN74ALS568A decade counter and

′ALS569A binary counters are programmable,

count up or down, and offer both synchronous and

asynchronous clearing. All synchronous functions

are executed on the positive-going edge of the

clock (CLK) input.

SN54ALS569A . . . FK PACKAGE

(TOP VIEW)

The clear function is initiated by applying a low

level to either asynchronous clear (ACLR) or

synchronousclear(SCLR). Asynchronous(direct)

clearing overrides all other functions of the device,

while synchronous clearing overrides only the

other synchronous functions. Data is loaded from

the A, B, C, and D inputs by holding load (LOAD)

low during a positive-going clock transition. The

counting function is enabled only when enable P

(ENP) and enable T (ENT) are low and ACLR,

SCLR, and LOAD are high. The up/down (U/D)

input controls the direction of the count. These

counters count up when U/D is high and count

down when U/D is low.

20 19

CCO

ENP

ACLR

9 10 11 12 13

A high level at the output-enable (OE) input forces the Q outputs into the high-impedance state, and a low level

enables those outputs. Counting is independent of OE. ENT is fed forward to enable the ripple-carry output

(RCO) to produce a low-level pulse while the count is zero (all Q outputs low) when counting down or maximum

(9 or 15) when counting up. The clocked carry output (CCO) produces a low-level pulse for a duration equal to

that of the low level of the clock when RCO is low and the counter is enabled (both ENP and ENT are low);

otherwise, CCO is high. CCO does not have the glitches commonly associated with a ripple-carry output.

Cascading is normally accomplished by connecting RCO or CCO of the first counter to ENT of the next counter.

However, for very high-speed counting, RCO should be used for cascading since CCO does not become active

until the clock returns to the low level.

The SN54ALS569A is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ALS568A and SN74ALS569A are characterized for operation from 0°C to 70°C.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...20

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8302502RA 替代型号

型号	品牌	替代类型	描述	数据表
SNJ54ALS569AJ	TI	完全替代	SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS WITH 3-STATE OUTPUTS
SN74ALS569ANE4	TI	类似代替	SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS WITH 3-STATE OUTPUTS
SN74ALS569AN	TI	类似代替	SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS WITH 3-STATE OUTPUTS

与8302502RA相关器件

型号	品牌	获取价格	描述	数据表
8302502RX	ETC	获取价格	Synchronous Up/Down Counter
8302502SA	TI	获取价格	SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS WITH 3-STATE OUTPUTS
8302502SX	ETC	获取价格	Synchronous Up/Down Counter
83026AIL	ICSI	获取价格	LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
83026AMI	ICSI	获取价格	LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
83026AMILF	IDT	获取价格	Differential-to-LVCMOS/LVTTL Fanout
83026AMILFT	IDT	获取价格	Differential-to-LVCMOS/LVTTL Fanout
83026BGI-01	IDT	获取价格	Low Skew Clock Driver, 83026 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 4.40 X
83026BGI-01LF	IDT	获取价格	Differential-to-LVCMOS/LVTTL Fanout Buffer
83026BGI-01LFT	IDT	获取价格	Differential-to-LVCMOS/LVTTL Fanout Buffer

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