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83026BMI-01 PDF预览

83026BMI-01

更新时间: 2024-11-24 20:57:15
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
15页 341K
描述
Low Skew Clock Driver, 83026 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3.80 X 4.80 MM, 1.47 MM HEIGHT, MS-012, SOIC-8

83026BMI-01 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:3.80 X 4.80 MM, 1.47 MM HEIGHT, MS-012, SOIC-8针数:8
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.53
系列:83026输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:8
实输出次数:2最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
电源:3.3 VProp。Delay @ Nom-Sup:3.1 ns
传播延迟(tpd):3.1 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.015 ns座面最大高度:1.75 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
最小 fmax:350 MHzBase Number Matches:1

83026BMI-01 数据手册

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ICS83026I-01  
LOW SKEW, 1-TO-2  
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS83026I-01 is a low skew, 1-to-2 Differential-to- Two LVCMOS / LVTTL outputs  
LVCMOS/LVTTL Fanout Buffer. The differential input can  
accept most differential signal types (LVPECL, LVDS,  
Differential CLK, nCLK input pair  
LVHSTL, HCSL and SSTL) and translate to two single-  
ended LVCMOS/LVTTL outputs. The small 8-lead SOIC  
footprint makes this device ideal for use in applications  
with limited board space.  
CLK, nCLK pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL  
Maximum output frequency: 350MHz  
Output skew: 15ps (maximum)  
Part-to-part skew: 600ps (maximum)  
Additive phase jitter, RMS: 0.03ps (typical)  
Small 8 lead SOIC package saves board space  
3.3V core, 3.3V, 2.5V or 1.8V output operating supply  
-40°C to 85°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free RoHS  
(6) packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VDD  
CLK  
nCLK  
OE  
VDDO  
Q0  
1
2
3
4
8
7
6
5
Q1  
GND  
Q0  
CLK  
nCLK  
Q1  
ICS83026I-01  
8-Lead SOIC  
3.8mm x 4.8mm, x 1.47mm package body  
M Package  
OE  
Top View  
VDD  
CLK  
nCLK  
OE  
VDDO  
Q0  
1
2
3
4
8
7
6
5
Q1  
GND  
ICS83026I-01  
8-Lead TSSOP  
4.40mm x 3.0mm x 0.925mm  
package body  
G Package  
Top View  
83026BMI-01  
1
REV. A AUGUST 4, 2010  

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