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83026I-01 PDF预览

83026I-01

更新时间: 2024-11-25 14:58:07
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
16页 366K
描述
Low Skew,1-to-2 Differential-to-LVCMOS/LVTTL Fanout Buffer

83026I-01 数据手册

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Low Skew, 1-to-2  
Differential-to-LVCMOS/LVTTL Fanout Buffer  
83026I-01  
Data Sheet  
GENERAL DESCRIPTION  
FEATURES  
The 83026I-01 is a low skew, 1-to-2 Differential-to-LVC- Two LVCMOS / LVTTL outputs  
MOS/LVTTL Fanout Buffer. The differential input can  
accept most differential signal types (LVPECL, LVDS,  
Differential CLK, nCLK input pair  
LVHSTL, HCSL and SSTL) and translate to two sin-  
gle-ended LVCMOS/LVTTL outputs. The small 8-lead SOIC  
footprint makes this device ideal for use in applications with  
limited board space.  
CLK, nCLK pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL  
Maximum output frequency: 350MHz  
Output skew: 15ps (maximum)  
Part-to-part skew: 600ps (maximum)  
Additive phase jitter, RMS: 0.03ps (typical)  
Small 8 lead SOIC package saves board space  
3.3V core, 3.3V, 2.5V or 1.8V output operating supply  
-40°C to 85°C ambient operating temperature  
Available in lead-free RoHS (6) package  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VDD  
CLK  
nCLK  
OE  
VDDO  
Q0  
1
2
3
4
8
7
6
5
Q1  
GND  
Q0  
CLK  
nCLK  
Q1  
83026I-01  
8-Lead SOIC  
3.8mm x 4.8mm, x 1.47mm package body  
M Package  
OE  
Top View  
VDD  
CLK  
nCLK  
OE  
VDDO  
Q0  
1
2
3
4
8
7
6
5
Q1  
GND  
83026I-01  
8-Lead TSSOP  
4.40mm x 3.0mm x 0.925mm  
package body  
G Package  
Top View  
1
December 15, 2015  

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