VCXO Jitter Attenuator &
813N252I-09
®
Datasheet
FemtoClock Multiplier
General Description
Features
The 813N252I-09 is a PLL based synchronous multiplier that is
optimized for PDH or SONET to Ethernet clock jitter attenuation and
frequency translation. The device contains two internal frequency
multiplication stages that are cascaded in series. The first stage is a
VCXO PLL that is optimized to provide reference clock jitter
attenuation. The second stage is a FemtoClock™frequency multiplier
that provides the low jitter, high frequency Ethernet output clock that
easily meets Gigabit and 10 Gigabit Ethernet jitter requirements.
Pre-divider and output divider multiplication ratios are selected using
device selection control pins. The multiplication ratios are optimized
to support most common clock rates used in PDH, SONET and
Ethernet applications. The VCXO requires the use of an external,
inexpensive pullable crystal. The VCXO uses external passive loop
filter components which allows configuration of the PLL loop
bandwidth and damping characteristics. The device is packaged in a
space-saving 32-VFQFN package and supports industrial
temperature range.
• Two LVPECL output pairs
Each output supports independent frequency selection at 25MHz,
125MHz, 156.25MHz and 312.5MHz
• Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, SSTL, HCSL
• Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
• Attenuates the phase jitter of the input clock by using a low-cost
pullable fundamental mode VCXO crystal
• VCXO PLL bandwidth can be optimized for jitter attenuation and
reference tracking using external loop filter connection
• FemtoClock frequency multiplier provides low jitter, high frequency
output
• Absolute pull range: 50ppm
• FemtoClock VCO frequency: 625MHz
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(12kHz – 20MHz): 0.25ps (typical) and 0.35ps (maximum)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Pin Assignment
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
LF1
LF0
VEE
24
23
22
21
20
nQB
QB
ISET
VCCO
nQA
VEE
CLK_SEL
VCC
QA
19
18
17
RESERVED
VEE
VEE
ODASEL_0
9
10 11 12 13 14 15 16
813N252I-09
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm EPad
K Package
Top View
©2015 Integrated Device Technology, Inc.
1
Revision C, December 10, 2015