Advanced Datasheet
80KSBR200
sRIO SERIAL BUFFER
FLOW-CONTROL DEVICE
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Programmable Target Address
Device Overview
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Packet Tally Indicator
Packet Interval Timer
Replace Missing Packet
The IDT80KSBR200 is a high speed Serial Buffer (SerB) that can
connect to any Serial RapidIO compliant interface. This device is built to
work with any sRIO device and especially with the IDT Pre-Processing
Switch (PPS), IDT70K200. The SerB performs buffering and off-loading
of data as well as buffer-delay of data samples in various environments.
This device primarily acts as an master in which the SerB bursts data to
a programmed memory location once some criteria have been meet.
This combination of storage and flexibility make it the perfect buffering
solution for sRIO systems.
Optional External QDR SRAM Available
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Up to 72Mbit external QDR SRAM
QDR SRAM, 200 MHz; (18M, 36M, 72M)
Seamless Integration of Internal and External Memory
Internal and external memory functions as a single buffer
Single Port Buffering
Status Flags for Combined Internal/External Memories
Full, Empty, Partially Empty, Partially Full
Direct or polled operation of flag status bus
Optional Watermark
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Serial Buffer can Either Send a Flag or Transmit Data at a Specific Packet
Features
Count
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Interface - I2C Interface Port
Serial RapidIO Port
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2
Interface - sRIO
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One I C port for maintenance and error reporting
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One four-lane (4x) link, configurable to one-lane (1x) link
Port Speeds selectable: 3.125 Gbps, 2.5 Gbps, or 1.25 Gbps
Short haul or long haul reach for each PHY speed
Support 8-bit and 16-bit deviceID
Error management supports standard
sRIO version 1.3
Class 1+ End Point Device
Interface - JTAG Interface
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JTAG Functionality for boundary scan and programming
High-Speed CMOS Technology
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1.2V Core operation with 3.3/2.5V JTAG interface
Package: 484-pin Plastic Ball Grid Array
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23mm x 23mm, 1.0mm ball pitch
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10 Gbps Throughput
18Mbit Internal Density
Block Diagram
S-Port 1
1x/4x sRIO
Interface
Queue 0
18 Mbits
TCK
TMS
TDI
TDO
SCL
SDA
Configuration
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Flag Registers
2
PHY Clk
QDR Clk
MR
FR
Flags
8
2
P-Port
2
2
drw01 DSC-6730
Hardwire
Config
K/K CQ
CQ
A Rd Wr
D
Q
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.