74V1G79

更新时间： 2024-11-03 22:45:59

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		触发器
页数	文件大小	规格书
10页	203K
描述
SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP

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中文翻译

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数据手册

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74V1G79 数据手册

74V1G79

SINGLE POSITIVE EDGE TRIGGERED

D-TYPE FLIP-FLOP

■

HIGH SPEED:

= 180MHz (TYP.) at V = 5V

MAX

LOW POWER DISSIPATION:

= 1µA(MAX.) at T =25°C

HIGH NOISE IMMUNITY:

= V = 28% V (MIN.)

NIH

NIL

SOT23-5L

SOT323-5L

T & R

■

POWER DOWN PROTECTION ON INPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 8mA (MIN) at V = 4.5V

■

BALANCED PROPAGATION DELAYS:

ORDER CODES

PLH

PHL

PACKAGE

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 5.5V

SOT23-5L

74V1G79STR

74V1G79CTR

SOT323-5L

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

Following the hold time interval, data at the D input

can be changed without affecting the level at the

output. Power down protection is provided on

inputs and 0 to 7V can be accepted on inputs with

no regard to the supply voltage. This device can

be used to interface 5V to 3V systems.

It’s available in the commercial and extended

temperature range. All inputs and output are

equipped with protection circuits against static

discharge, giving them ESD immunity and

transient excess voltage.

The 74V1G79 is an advanced high-speed CMOS

SINGLE POSITIVE EDGE TRIGGERED D-TYPE

FLIP-FLOP fabricated with sub-micron silicon

gate and double-layer metal wiring C MOS

technology. it is designed to operate from 2V to

5.5V, making this device ideal for portable

applications.

This D-Type flip-flop is controlled by a clock input

(CK). On the positive transition of the clock, the Q

output will be set to the logic state that was setup

at the D input.

PIN CONNECTION AND IEC LOGIC SYMBOLS

July 2001

1/10

12 3 4 5 6 7...10

中文翻译

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74V1G79CTR	STMICROELECTRONICS	获取价格	SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
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