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74V1T03 PDF预览

74V1T03

更新时间: 2024-11-03 22:10:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输入元件
页数 文件大小 规格书
7页 51K
描述
SINGLE 2-INPUT OPEN DRAIN NAND GATE

74V1T03 数据手册

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74V1T03  
SINGLE 2-INPUT OPEN DRAIN NAND GATE  
PRELIMINARY DATA  
HIGH SPEED:tPD =7 ns (TYP.) atVCC =5V  
LOW POWER DISSIPATION:  
CC =1 µA (MAX.) at TA =25 oC  
I
COMPATIBLEWITH TTL OUTPUTS:  
VIH =2V (MIN), VIL = 0.8V(MAX)  
S
C
POWERDOWN PROTECTIONON INPUTS  
OPERATING VOLTAGERANGE:  
(SOT23-5L)  
(SC-70)  
ORDER CODE:  
VCC (OPR)= 4.5V to 5.5V  
74V1T03S  
74V1T03C  
IMPROVED LATCH-UP IMMUNITY  
This device can, with an external pull-up resistor,  
be used in wired AND configuration. This device  
can also be used as a led driver in any other  
application requiring a current sink.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface5V to 3V.  
DESCRIPTION  
The 74V1T03 is an advanced high-speed CMOS  
SINGLE 2-INPUT OPEN DRAIN NAND GATE  
fabricated with sub-micron silicon gate and  
double-layermetal wiring C2MOS technology.  
The internal circuit is composed of 3 stages  
including buffer output, which provide high noise  
immunity and stable output.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/7  
September 1999  

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