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74LVX573SJX PDF预览

74LVX573SJX

更新时间: 2024-01-13 05:23:38
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器逻辑集成电路光电二极管驱动
页数 文件大小 规格书
7页 95K
描述
Low Voltage Octal Latch with 3-STATE Outputs

74LVX573SJX 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP20,.25
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.14
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:6.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.004 A湿度敏感等级:3
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
电源:3.3 VProp。Delay @ Nom-Sup:14.5 ns
传播延迟(tpd):22 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

74LVX573SJX 数据手册

 浏览型号74LVX573SJX的Datasheet PDF文件第1页浏览型号74LVX573SJX的Datasheet PDF文件第2页浏览型号74LVX573SJX的Datasheet PDF文件第3页浏览型号74LVX573SJX的Datasheet PDF文件第5页浏览型号74LVX573SJX的Datasheet PDF文件第6页浏览型号74LVX573SJX的Datasheet PDF文件第7页 
AC Electrical Characteristics  
V
T
25 C  
Typ  
T
40 C to 85 C  
Min  
CC  
A
A
Symbol  
Parameter  
Units  
Conditions  
15 pF  
(V)  
Min  
Max  
14.5  
18.0  
9.3  
Max  
17.5  
21.0  
11.0  
14.5  
18.5  
22.0  
12.0  
15.5  
18.5  
22.0  
12.0  
15.5  
22.0  
15.5  
t
t
Propagation  
Delay Time  
to O  
2.7  
7.6  
10.1  
5.9  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
7.5  
5.0  
5.0  
3.5  
1.5  
1.5  
C
C
C
C
C
C
C
C
C
C
C
C
C
C
PLH  
PHL  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
50 pF  
ns  
D
3.3 0.3  
2.7  
15 pF  
n
n
8.4  
12.8  
15.6  
19.1  
10.1  
13.6  
15.0  
18.5  
9.7  
50 pF  
t
t
Propagation  
Delay Time  
8.2  
15 pF  
PLH  
PHL  
10.7  
6.4  
50 pF  
ns  
ns  
LE to O  
3.3 0.3  
2.7  
15 pF  
n
8.9  
50 pF  
t
t
3-STATE Output  
Enable Time  
7.8  
15 pF, R  
50 pF, R  
15 pF, R  
50 pF, R  
50 pF, R  
50 pF, R  
1 k  
1 k  
1 k  
1 k  
1 k  
1 k  
PZL  
PZH  
L
L
L
L
L
L
10.3  
6.1  
3.3 0.3  
8.6  
13.2  
19.1  
13.6  
t
t
t
3-STATE Output  
Disable Time  
LE Pulse  
2.7  
3.3 0.3  
2.7  
12.1  
10.1  
PLZ  
PHZ  
W
ns  
ns  
ns  
ns  
ns  
6.5  
5.0  
5.0  
3.5  
1.5  
1.5  
Width  
3.3 0.3  
2.7  
t
t
Setup Time  
S
H
D
to LE  
3.3 0.3  
2.7  
n
Hold Time  
to LE  
D
3.3 0.3  
2.7  
n
t
t
Output to Output  
Skew (Note 4)  
1.5  
1.5  
1.5  
1.5  
C
50 pF  
OSHL  
OSLH  
L
2.3  
Note 4: Parameter guaranteed by design. t  
|t  
t
|, t  
|t  
t
|.  
PHLn  
OSLH  
PLHm  
PLHn OSHL  
PHLm  
Capacitance  
T
25 C  
Typ  
T
40 C to 85 C  
A
A
Symbol  
Parameter  
Units  
Min  
Max  
10  
Min  
Max  
C
Input Capacitance  
Output Capacitance  
Power Dissipation  
Capacitance (Note 5)  
4
6
10  
pF  
pF  
pF  
IN  
C
OUT  
PD  
C
27  
Note 5: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.  
PD  
www.fairchildsemi.com  
4

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