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74LVX573SJX PDF预览

74LVX573SJX

更新时间: 2024-01-19 05:02:12
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器逻辑集成电路光电二极管驱动
页数 文件大小 规格书
7页 95K
描述
Low Voltage Octal Latch with 3-STATE Outputs

74LVX573SJX 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP20,.25
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.14
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:6.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.004 A湿度敏感等级:3
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
电源:3.3 VProp。Delay @ Nom-Sup:14.5 ns
传播延迟(tpd):22 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

74LVX573SJX 数据手册

 浏览型号74LVX573SJX的Datasheet PDF文件第1页浏览型号74LVX573SJX的Datasheet PDF文件第3页浏览型号74LVX573SJX的Datasheet PDF文件第4页浏览型号74LVX573SJX的Datasheet PDF文件第5页浏览型号74LVX573SJX的Datasheet PDF文件第6页浏览型号74LVX573SJX的Datasheet PDF文件第7页 
Functional Description  
Truth Table  
The LVX573 contains eight D-type latches. When the  
enable (LE) input is HIGH, data on the Dn inputs enters the  
Inputs  
Outputs  
On  
latches. In this condition the latches are transparent, i.e., a  
OE  
L
LE  
H
H
L
D
H
L
latch output will change state each time its  
D input  
changes. When LE is LOW the latches store the informa-  
tion that was present on the D inputs a setup time preced-  
ing the HIGH-to-LOW transition of LE. The 3-STATE  
buffers are controlled by the Output Enable (OE) input.  
When OE is LOW, the buffers are enabled. When OE is  
HIGH the buffers are in the high impedance mode but this  
does not interfere with entering new data into the latches.  
H
L
L
L
X
X
O0  
Z
H
X
H
L
Z
X
O
HIGH Voltage  
LOW Voltage  
High Impedance  
Immaterial  
Previous O before HIGH-to-LOW transition of Latch Enable  
0
0
Logic Diagram  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
www.fairchildsemi.com  
2

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