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74LVX373T PDF预览

74LVX373T

更新时间: 2024-11-13 23:24:31
品牌 Logo 应用领域
其他 - ETC 锁存器
页数 文件大小 规格书
10页 78K
描述
8-Bit D-Type Latch

74LVX373T 数据手册

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74LVX373  
LOW VOLTAGE OCTAL D-TYPE LATCH  
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS  
HIGH SPEED:tPD =5.8ns (TYP.) atVCC = 3.3V  
5V TOLERANT INPUTS  
POWER-DOWN PROTECTIONON INPUTS  
INPUT VOLTAGELEVEL:  
VIL =0.8V,VIH =2V atVCC =3V  
LOW POWER DISSIPATION:  
I
M
T
(Micro Package)  
(TSSOPPackage)  
CC =4 µA (MAX.) at TA =25 oC  
ORDER CODES :  
LOWNOISE:  
OLP =0.3 V (TYP.)at VCC = 3.3V  
74LVX373M  
74LVX373T  
V
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 4 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
While the LE input is held at a high level, the Q  
outputswill follow the data input precisely.  
When the LE is taken low, the Q outputs will be  
latched precisely at the logic level of D input data.  
While the (OE) input is low, the 8 outputs will be  
in a normal logic state (high or low logic level)  
and while high level the outputs will be in a high  
impedance state.  
It has better speed performance at 3.3V than 5V  
LS-TTL family combined with the true CMOS low  
power consuption.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface5V to 3V.  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 3.6V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES373  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The LVX373 is a low voltage CMOS OCTAL  
D-TYPE LATCH with 3 STATE OUTPUT NON  
INVERTING fabricated with sub-micron silicon  
gate and double-layer metal wiring C2MOS  
technology.It is ideal for low power and low noise  
3.3V applications.  
This 8 bit D-Type latch is controlled by a latch  
enable input (LE) and an output enable input  
(OE).  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/10  
May 1999  

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