74LVX374
LOW VOLTAGE OCTAL D-TYPE FLIP FLOP
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
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HIGH SPEED:
MAX =160MHz(TYP.) at VCC =3.3V
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5V TOLERANT INPUTS
POWER-DOWN PROTECTIONON INPUTS
INPUT VOLTAGELEVEL:
VIL =0.8V,VIH =2V atVCC =3V
LOW POWER DISSIPATION:
ICC =4 µA (MAX.) at TA =25 oC
LOWNOISE:
M
T
(Micro Package)
(TSSOPPackage)
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ORDER CODES :
74LVX374M
74LVX374T
VOLP =0.3 V (TYP.)at VCC = 3.3V
outputs will be set to the logic state that were
setup at the D inputs.
While the (OE) input is low, the 8 outputs will be
in a normal state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
The output control does not affect the internal
operation of flip flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4 mA (MIN)
BALANCEDPROPAGATIONDELAYS:
tPLH tPHL
OPERATING VOLTAGERANGE:
VCC (OPR)= 2V to 3.6V
PIN AND FUNCTION COMPATIBLEWITH
74 SERIES374
IMPROVED LATCH-UP IMMUNITY
It has better speed performance at 3.3V than 5V
LSTTL family combined with the true CMOS low
power consumption.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The LVX374 is a low voltage CMOS OCTAL
D-TYPE FLIP FLOP with 3 STATE OUTPUT
NON INVERTING fabricated with sub-micron
silicon gate and double-layermetal wiring C2MOS
technology.It is ideal for low power and low noise
applications.
This 8 bit D-Type flip-flop is controlled by a clock
input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/10
April 1999