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74LVX374M PDF预览

74LVX374M

更新时间: 2024-11-13 22:53:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 95K
描述
Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

74LVX374M 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP20,.4针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.13
Is Samacsys:N系列:LV/LV-A/LVX/H
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.8015 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:55000000 Hz
最大I(ol):0.004 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:16 ns
传播延迟(tpd):23 ns认证状态:Not Qualified
座面最大高度:2.642 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:7.493 mmBase Number Matches:1

74LVX374M 数据手册

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October 1993  
Revised April 2005  
74LVX374  
Low Voltage Octal D-Type Flip-Flop with  
3-STATE Outputs  
General Description  
Features  
Input voltage translation from 5V to 3V  
The LVX374 is a high-speed, low-power octal D-type flip-  
flop featuring separate D-type inputs for each flip-flop and  
3-STATE outputs for bus-oriented applications. A buffered  
Clock (CP) and Output Enable (OE) are common to all flip-  
flops. The inputs tolerate up to 7V allowing interface of 5V  
systems to 3V systems.  
Ideal for low power/low noise 3.3V applications  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVX374M  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LVX374SJ  
74LVX374MTC  
MTC20  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
Description  
D0D7  
CP  
Data Inputs  
Clock Pulse Input  
OE  
3-STATE Output Enable Input  
3-STATE Outputs  
O0O7  
© 2005 Fairchild Semiconductor Corporation  
DS011612  
www.fairchildsemi.com  

74LVX374M 替代型号

型号 品牌 替代类型 描述 数据表
SN74LV374ADW TI

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SN74LV374ADBR TI

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OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS

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