Datasheet > 74LVX27_04

74LVX27_04

更新时间： 2024-11-29 04:47:59

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		输入元件
页数	文件大小	规格书
11页	216K
描述
LOW VOLTAGE CMOS TRIPLE 3-INPUT NOR GATE WITH 5V TOLERANT INPUTS

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74LVX27_04 数据手册

74LVX27

LOW VOLTAGE CMOS TRIPLE 3-INPUT NOR GATE

WITH 5V TOLERANT INPUTS

■

HIGH SPEED:

= 4.1ns (TYP.) at V = 3.3V

■

5V TOLERANT INPUTS

INPUT VOLTAGE LEVEL:

V =0.8V, V =2V at V =3V

■

LOW POWER DISSIPATION:

= 2 µA (MAX.) at T =25°C

SOP

TSSOP

LOW NOISE:

= 0.3V (TYP.) at V = 3.3V

Table 1: Order Codes

PACKAGE

OLP

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 4mA (MIN)

T & R

SOP

74LVX27MTR

74LVX27TTR

BALANCED PROPAGATION DELAYS:

TSSOP

PLH

PHL

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 3.6V (1.2V Data Retention)

The internal circuit is composed of 3 stages

including buffer output, which provides high noise

immunity and stable output.

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 27

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage.

■

IMPROVED LATCH-UP IMMUNITY

POWER DOWN PROTECTION ON INPUTS

This device can be used to interface 5V to 3V

system. It combines high speed performance with

the true CMOS low power consumption.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

DESCRIPTION

The 74LVX27 is a low voltage CMOS TRIPLE

3-INPUT NOR GATE fabricated with sub-micron

silicon gate and double-layer metal wiring C MOS

technology. It is ideal for low power, battery

operated and low noise 3.3V applications.

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 3

1/11

August 2004

12 3 4 5 6 7...11

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