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74LVTH574MTCX_NL

更新时间： 2024-01-06 05:58:32
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飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
8页 111K
描述
Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

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中文翻译

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74LVTH574MTCX_NL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP,针数：20
Reach Compliance Code：unknown风险等级：5.15
Is Samacsys：N其他特性：BROADSIDE VERSION OF 374
系列：LVTJESD-30 代码：R-PDSO-G20
JESD-609代码：e3长度：12.8015 mm
逻辑集成电路类型：BUS DRIVER湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260传播延迟（tpd）：5.3 ns
座面最大高度：2.642 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.493 mmBase Number Matches：1

74LVTH574MTCX_NL 数据手册

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March 1999  
Revised March 2005  
74LVT574 • 74LVTH574  
Low Voltage Octal D-Type Flip-Flop  
with 3-STATE Outputs  
General Description  
Features  
■ Input and output interface capability to systems at  
The LVT574 and LVTH574 are high-speed, low-power  
octal D-type flip-flop featuring separate D-type inputs for  
each flip-flop and 3-STATE outputs for bus-oriented appli-  
cations. A buffered Clock (CP) and Output Enable (OE) are  
common to all flip-flops.  
5V VCC  
■ Bushold data inputs eliminate the need for external  
pull-up resistors to hold unused inputs (74LVTH574),  
also available without bushold feature (74LVT574)  
The LVTH574 data inputs include bushold, eliminating the  
need for external pull-up resistors to hold unused inputs.  
■ Live insertion/extraction permitted  
■ Power Up/Down high impedance provides glitch-free  
bus loading  
These octal flip-flops are designed for low-voltage (3.3V)  
VCC applications, but with the capability to provide a TTL  
■ Outputs source/sink 32 mA/ 64 mA  
■ Functionally compatible with the 74 series 574  
■ Latch-up performance exceeds 500 mA  
■ ESD performance:  
interface to a 5V environment. The LVT574 and LVTH574  
are fabricated with an advanced BiCMOS technology to  
achieve high speed operation similar to 5V ABT while  
maintaining a low power dissipation.  
Human-body model 2000V  
Machine model 200V  
Charged-device model 1000V  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74LVT574WM  
74LVT574SJ  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LVT574MSA  
74LVT574MTC  
MSA20  
MTC20  
MTC20  
74LVT574MTCX_NL  
(Note 1)  
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
74LVTH574WM  
74LVTH574SJ  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LVTH574MSA  
74LVTH574MTC  
MSA20  
MTC20  
MTC20  
74LVTH574MTCX_NL  
(Note 1)  
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
© 2005 Fairchild Semiconductor Corporation  
DS012451  
www.fairchildsemi.com  
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