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74LVTH646 PDF预览

74LVTH646

更新时间: 2024-11-10 22:56:23
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飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
8页 81K
描述
Low Voltage Octal Transceiver/Register with 3-STATE Outputs

74LVTH646 数据手册

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November 1999  
Revised May 2000  
74LVTH646  
Low Voltage Octal Transceiver/Register  
with 3-STATE Outputs  
General Description  
Features  
Input and output interface capability to systems at  
The LVTH646 consists of registered bus transceiver cir-  
cuits, D-type flip-flops, and control circuitry providing multi-  
plexed transmission of data directly from the input bus or  
from the internal storage registers. Data on the A or B bus  
will be loaded into the respective registers on the LOW-to-  
HIGH transition of the appropriate clock pin (CPAB or  
CPBA). (See Functional Description)  
5V VCC  
Bushold data inputs eliminate the need for external  
pull-up resistors to hold unused inputs  
Live insertion/extraction permitted  
Power Up/Down high impedance provides glitch-free  
bus loading  
The LVTH646 data inputs include bushold, eliminating the  
need for external pull-up resistors to hold unused inputs.  
Outputs source/sink 32 mA/+64 mA  
Functionally compatible with the 74 series 646  
Latch-up performance exceeds 500 mA  
The bus transceivers are designed for low-voltage (3.3V)  
VCC applications, but with the capability to provide a TTL  
interface to a 5V environment. The LVTH646 is fabricated  
with an advanced BiCMOS technology to achieve high  
speed operation similar to 5V ABT while maintaining low  
power dissipation.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVTH646WM  
M24B  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide  
74LVTH646MTC  
MTC24  
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code.  
Logic Symbols  
IEEE/IEC  
© 2000 Fairchild Semiconductor Corporation  
DS012017  
www.fairchildsemi.com  

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