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74LVTH182652APMG4 PDF预览

74LVTH182652APMG4

更新时间： 2024-11-09 14:47:07
品牌 Logo 应用领域
德州仪器 - TI 信息通信管理输出元件逻辑集成电路触发器
页数 文件大小 规格书
38页 602K
描述
LVT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64, GREEN, PLASTIC, LQFP-64

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74LVTH182652APMG4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LFQFP, QFP64,.47SQ,20针数：64
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.62Is Samacsys：N
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：LVTJESD-30 代码：S-PQFP-G64
JESD-609代码：e4长度：10 mm
逻辑集成电路类型：BOUNDARY SCAN REG BUS TRANSCEIVER最大I（ol）：0.064 A
湿度敏感等级：3位数：9
功能数量：2端口数量：2
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP64,.47SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：8 ns传播延迟（tpd）：8.2 ns
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：POSITIVE EDGE
宽度：10 mmBase Number Matches：1

74LVTH182652APMG4 数据手册

 浏览型号74LVTH182652APMG4的Datasheet PDF文件第2页浏览型号74LVTH182652APMG4的Datasheet PDF文件第3页浏览型号74LVTH182652APMG4的Datasheet PDF文件第4页浏览型号74LVTH182652APMG4的Datasheet PDF文件第5页浏览型号74LVTH182652APMG4的Datasheet PDF文件第6页浏览型号74LVTH182652APMG4的Datasheet PDF文件第7页 
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A  
3.3-V ABT SCAN TEST DEVICES  
WITH 18-BIT TRANSCEIVERS AND REGISTERS  
SCBS312C – MARCH 1994 – REVISED JUNE 1997  
Members of the Texas Instruments  
SCOPE Family of Testability Products  
Compatible With the IEEE Std 1149.1-1990  
(JTAG) Test Access Port and  
Boundary-Scan Architecture  
Members of the Texas Instruments  
Widebus Family  
SCOPE Instruction Set  
– IEEE Std 1149.1-1990 Required  
Instructions and Optional CLAMP and  
HIGHZ  
– Parallel-Signature Analysis at Inputs  
– Pseudo-Random Pattern Generation  
From Outputs  
– Sample Inputs/Toggle Outputs  
– Binary Count From Outputs  
– Device Identification  
State-of-the-Art 3.3-V ABT Design Supports  
Mixed-Mode Signal Operation (5-V Input  
and Output Voltages With 3.3-V V  
)
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
Include D-Type Flip-Flops and Control  
Circuitry to Provide Multiplexed  
Transmission of Stored and Real-Time Data  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
– Even-Parity Opcodes  
Packaged in 64-Pin Plastic Thin Quad Flat  
(PM) Packages Using 0.5-mm  
B-Port Outputs of ’LVTH182652A Devices  
Have Equivalent 25-Ω Series Resistors, So  
No External Resistors Are Required  
Center-to-Center Spacings and 68-Pin  
Ceramic Quad Flat (HV) Packages Using  
25-mil Center-to-Center Spacings  
description  
The ’LVTH18652A and ’LVTH182652A scan test devices with 18-bit bus transceivers and registers are  
members of the Texas Instruments (TI) SCOPE testability integrated-circuit family. This family of devices  
supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan  
access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.  
Additionally, these devices are designed specifically for low-voltage (3.3-V) V  
capability to provide a TTL interface to a 5-V system environment.  
operation, but with the  
CC  
In the normal mode, these devices are 18-bit bus transceivers and registers that allow for multiplexed  
transmission of data directly from the input bus or from the internal registers. They can be used either as two  
9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot  
samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating  
the TAP in the normal mode does not affect the functional operation of the SCOPE bus transceivers  
and registers.  
Data flow in each direction is controlled by clock (CLKAB and CLKBA), select (SAB and SBA), and  
output-enable (OEAB and OEBA) inputs. For A-to-B data flow, data on the A bus is clocked into the associated  
registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation  
to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus  
(registered mode). When OEAB is high, the B outputs are active. When OEAB is low, the B outputs are in the  
high-impedance state.  
Control for B-to-A data flow is similar to that for A-to-B data flow but uses CLKBA, SBA, and OEBA inputs. Since  
the OEBA input is active-low, the A outputs are active when OEBA is low and are in the high-impedance state  
when OEBA is high. Figure 1 illustrates the four fundamental bus-management functions that can be performed  
with the ’LVTH18652A and ’LVTH182652A.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...38

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74LVTH182652APMG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVTH182652APM TI

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